Alternatives and similar repositories for MAPP

Users that are interested in MAPP are comparing it to the libraries listed below

• dwarning / VA-Models
  Verilog-A simulation models
  ☆72Updated last week
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆80Updated last month
• jaijeet / VAPP
  The Berkeley Verilog-A Parser and Processor
  ☆14Updated 8 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 10 months ago
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 7 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆38Updated 2 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆40Updated last year
• MatBucher / ekv3model
  ☆18Updated last year
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆100Updated 2 years ago
• mabrains / gdsfactory-generic-pdk
  Generic Process Design Kit for Gdsfactory
  ☆20Updated last year
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆36Updated 5 years ago
• zwh42 / KLayout-PyMacros
  Python library for KLayout (https://www.klayout.de/)
  ☆24Updated 5 years ago
• fsitok / gds3xtrude
  Simple 3D layout viewer for KLayout (Salt package)
  ☆20Updated 6 years ago
• proppy / rad-lab
  ☆12Updated 2 years ago
• cogenda / VA-BSIM48
  Verilog-A implementation of MOSFET model BSIM4.8
  ☆13Updated 5 years ago
• ucb-art / bag
  BAG framework
  ☆29Updated 5 months ago
• google / bigspicy
  ☆41Updated 2 years ago
• idea-fasoc / fasoc
  ☆54Updated last year
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆119Updated 2 years ago
• BerkeleyPhotonicsGenerator / BPG
  The Berkeley Photonics Generator (BPG) is a Python framework that enables the generation and simulation of photonics layout
  ☆36Updated 9 months ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆28Updated 3 weeks ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆31Updated 3 weeks ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆24Updated 2 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆54Updated this week
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated 11 months ago
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆33Updated 2 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• kadomoto / picture-to-gds
  Python script to convert image files to GDSII files
  ☆63Updated 3 months ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆117Updated 3 weeks ago