jaijeet / MAPPLinks
The Berkeley Model and Algorithm Prototyping Platform
☆21Updated last year
Alternatives and similar repositories for MAPP
Users that are interested in MAPP are comparing it to the libraries listed below
Sorting:
- The Berkeley Verilog-A Parser and Processor☆14Updated 8 years ago
- Verilog-A simulation models☆90Updated 2 months ago
- ADMS is a code generator for some of Verilog-A☆103Updated 3 years ago
- XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.☆178Updated last month
- skywater 130nm pdk☆40Updated last week
- repository for a bandgap voltage reference in SKY130 technology☆41Updated 2 years ago
- Simple 3D layout viewer for KLayout (Salt package)☆20Updated 6 years ago
- Fork from https://sourceforge.net/projects/gds3d☆68Updated last year
- Easy access to OpenSource TCAD Tools☆41Updated 2 weeks ago
- Hardware Description Library☆88Updated 9 months ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- BAG framework☆41Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆66Updated this week
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆55Updated 8 years ago
- Parsing and generating popular formats of circuit netlist☆39Updated 3 years ago
- A tiny Python package to parse spice raw data files.☆53Updated 3 years ago
- Interchange formats for chip design.☆36Updated this week
- ☆23Updated 5 years ago
- FastCap is the premium capacitance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastCap …☆50Updated 10 years ago
- Parasitic Extraction for KLayout☆36Updated last week
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆26Updated last year
- ☆95Updated 6 years ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆49Updated 4 months ago
- Automatic generation of real number models from analog circuits☆47Updated last year
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆127Updated last week
- ☆19Updated last year
- A simple but powerful Python package for creating photolithography masks in the GDSII format.☆95Updated 2 years ago
- Python script to convert image files to GDSII files☆69Updated 10 months ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆128Updated 2 years ago