☆27Mar 19, 2021Updated 5 years ago
Alternatives and similar repositories for OpenCompArchCourse
Users that are interested in OpenCompArchCourse are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 11 months ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 6 months ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- SystemVerilog implemention of the TAGE branch predictor☆14May 26, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 基4booth乘法器设计与验证☆15Apr 28, 2024Updated 2 years ago
- ☆24Dec 31, 2024Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 6 years ago
- A simple CPU ray tracer written in Rust☆22Mar 10, 2023Updated 3 years ago
- QuardStar Tutorial is all you need !☆17Sep 11, 2024Updated last year
- ☆21Mar 18, 2022Updated 4 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Mar 30, 2026Updated last month
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Feb 26, 2025Updated last year
- A novel FPGA-based intent recognition systemutilizing deep recurrent neural networks☆27Aug 25, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated 2 years ago
- A floating-point matrix multiplication implemented in hardware☆32Jan 5, 2021Updated 5 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆15Sep 17, 2019Updated 6 years ago
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated 11 months ago
- Pipelined 64-bit RISC-V core☆16Mar 7, 2024Updated 2 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆98Oct 17, 2025Updated 6 months ago
- FPGA implementation of an Apple//e (enhanced)☆16Mar 14, 2025Updated last year
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆26Dec 18, 2024Updated last year
- Championship Branch Prediction 2025☆69May 19, 2025Updated 11 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- hardware & software prefetcher☆30Dec 21, 2023Updated 2 years ago
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago
- Materials, slides, and workspace for the gem5 bootcamp 2024☆54Jan 23, 2026Updated 3 months ago
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- CMake based hardware build system☆38Apr 24, 2026Updated last week
- Research Artifact for HPCA'24 Paper: *Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities*.☆11Oct 30, 2025Updated 6 months ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Aug 7, 2021Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆102Mar 5, 2026Updated last month
- The Unified TileLink Memory Subsystem Tester for XiangShan☆14Apr 23, 2026Updated last week
- ☆27Jan 22, 2023Updated 3 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- ☆13Apr 15, 2025Updated last year
- ☆14Nov 23, 2020Updated 5 years ago