jieltan / OpenCompArchCourseLinks
☆24Updated 4 years ago
Alternatives and similar repositories for OpenCompArchCourse
Users that are interested in OpenCompArchCourse are comparing it to the libraries listed below
Sorting:
- Advanced Architecture Labs with CVA6☆71Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆61Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- BlackParrot on Zynq☆47Updated this week
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 3 weeks ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Updated last month
- An almost empty chisel project as a starting point for hardware design☆33Updated 10 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated last month
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆15Updated 3 years ago
- ☆60Updated 7 months ago
- ☆79Updated 11 years ago
- Template for project1 TPU☆21Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- matrix-coprocessor for RISC-V☆25Updated last week
- ☆28Updated 6 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated last week
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Public release☆58Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆73Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated this week
- HLS for Networks-on-Chip☆38Updated 4 years ago