Alternatives and similar repositories for OpenCompArchCourse

Users that are interested in OpenCompArchCourse are comparing it to the libraries listed below

• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆91Updated last month
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆60Updated last year
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• pulp-platform / ITA
  ☆51Updated 5 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 11 months ago
• jay16udani / ECE745_LC3_Verification
  North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog
  ☆11Updated 8 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆32Updated 5 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆33Updated 8 months ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆31Updated 3 years ago
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆22Updated 10 months ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆20Updated 5 months ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆67Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆48Updated last week
• black-parrot / black-parrot-sim
  ☆12Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 4 months ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆17Updated last year
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆78Updated 10 years ago
• riscv-admin / integrated-matrix-extension
  Administrative repository for the Integrated Matrix Extension Task Group
  ☆27Updated last week
• hyoukjun / OpenSMART
  Public release
  ☆56Updated 6 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆42Updated this week