LLM-aided Hardware Design and Verification
☆34May 11, 2026Updated 2 months ago
Alternatives and similar repositories for LLM4ChipDesign
Users that are interested in LLM4ChipDesign are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆16Mar 23, 2026Updated 3 months ago
- ☆16Nov 27, 2025Updated 7 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- ☆30Jan 30, 2025Updated last year
- ☆15Jul 25, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A curated, community-maintained list of ML/LLM research and tools for integrated-circuit design — across the full flow.☆20Jun 30, 2026Updated 3 weeks ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆40May 17, 2024Updated 2 years ago
- ☆23Mar 12, 2026Updated 4 months ago
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆15Jun 26, 2024Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆37Jun 19, 2026Updated last month
- Generative Benchmark for LLM-Aided Hardware Design☆29Jun 4, 2025Updated last year
- Hack@DAC 2021☆20Jul 24, 2024Updated last year
- This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. …☆24Mar 25, 2025Updated last year
- ☆49Apr 7, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Logarithmic DAC for AY8913 and SN76489 programmable sound generators (Done as part of Zero To ASIC Analog course)☆11Jun 1, 2024Updated 2 years ago
- ☆42Dec 21, 2025Updated 6 months ago
- ☆17Feb 9, 2022Updated 4 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- ☆17Apr 19, 2026Updated 3 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- ☆28Aug 18, 2025Updated 11 months ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 9 years ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆26Jun 9, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆42Jun 22, 2025Updated last year
- [IPSN 2024] Lifelong Intelligence Beyond the Edge using Hyperdimensional Computing☆14May 16, 2024Updated 2 years ago
- ☆15Jun 27, 2024Updated 2 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆96Jul 29, 2025Updated 11 months ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆25May 20, 2026Updated 2 months ago
- TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection☆23Oct 3, 2023Updated 2 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆52Apr 22, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆64Oct 28, 2024Updated last year
- Generative AI for Semiconductor Design: Engineering Assistant built with Bedrock, Knowledge Bases and Langchain☆29Jun 14, 2024Updated 2 years ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆31Jul 24, 2025Updated 11 months ago
- An android app consuming pixabay api.☆10Sep 26, 2022Updated 3 years ago
- Computer Architecture UIUC SP 2018☆15May 4, 2018Updated 8 years ago
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 7 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆18Aug 3, 2021Updated 4 years ago