gokulbalagopal / Verification-of-FIFO-using-SystemVerilogView external linksLinks
Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog. Created components like generator, driver, monitor, scoreboard, interface, environment, and testbench.
☆36Feb 6, 2019Updated 7 years ago
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