A RISC-V processor in system verilog
☆12Jul 9, 2020Updated 5 years ago
Alternatives and similar repositories for ncore
Users that are interested in ncore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 9 months ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- Repository for system verilog labs from cadence☆15Feb 9, 2020Updated 6 years ago
- Source code SP Flash Tool v5.1720 for MTK☆12Oct 10, 2020Updated 5 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- A Zephyr producer consumer app. - An HDLC link over UART streaming sinwave samples and a Zephyr application consuming them - zephyr rtos,…☆10Nov 22, 2023Updated 2 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆12Oct 8, 2017Updated 8 years ago
- Baremetal RISC-V examples with modern C++☆17May 31, 2025Updated 9 months ago
- zero-riscy CPU Core☆18Jun 10, 2018Updated 7 years ago
- GitHub Action allowing to run tests in the Renode framework☆21Jan 13, 2026Updated 2 months ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- UART design in SV and verification using UVM and SV☆53Nov 30, 2019Updated 6 years ago
- Muscle-machine interface☆12Jul 19, 2016Updated 9 years ago
- ☆11Oct 28, 2020Updated 5 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- ☆13Nov 14, 2023Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆24Feb 19, 2025Updated last year
- ☆13Jun 12, 2024Updated last year
- The Unified TileLink Memory Subsystem Tester for XiangShan☆12Mar 6, 2026Updated 2 weeks ago
- Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html☆11Feb 5, 2019Updated 7 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Source code of the paper "FirmRCA: Towards Post-Fuzzing Analysis on ARM Embedded Firmware with Efficient Event-based Fault Localization"☆13Jan 6, 2026Updated 2 months ago
- System Verilog and Emulation. Written all the five channels.☆35Mar 9, 2017Updated 9 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆30Jun 1, 2022Updated 3 years ago
- Low Density Parity Check Decoder☆19Sep 12, 2016Updated 9 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆41Apr 13, 2021Updated 4 years ago
- RISC-V System on Chip Template☆161Aug 18, 2025Updated 7 months ago
- MIPS R10000 architecture simulator with C++☆10Jun 8, 2023Updated 2 years ago
- Jumpstart your custom DNN accelerator today. This project holds scripts to build and start containers that can compile binaries to the ze…☆10Jun 17, 2020Updated 5 years ago
- Circuit analysis environment for Python☆61Sep 6, 2024Updated last year