cpehle / ncoreLinks
A RISC-V processor in system verilog
☆12Updated 5 years ago
Alternatives and similar repositories for ncore
Users that are interested in ncore are comparing it to the libraries listed below
Sorting:
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A SystemVerilog source file pickler.☆60Updated last year
- Repository for system verilog labs from cadence☆15Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISC-V Verification Interface☆135Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 2 months ago
- RISC-V System on Chip Template☆160Updated 5 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Updated 10 months ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆50Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆55Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆146Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated 3 weeks ago
- Test dashboard for verification features in Verilator☆29Updated this week
- An automatic clock gating utility☆52Updated 9 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- SystemVerilog synthesis tool☆226Updated 10 months ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated 3 weeks ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year