hdl / pyHDLParserLinks
Simple Python parser for extracting HDL (VHDL or Verilog) documentation
☆21Updated last year
Alternatives and similar repositories for pyHDLParser
Users that are interested in pyHDLParser are comparing it to the libraries listed below
Sorting:
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆26Updated last year
- A flexible and scalable development platform for modern FPGA projects.☆25Updated this week
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Making cocotb testbenches that bit easier☆29Updated 2 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆68Updated this week
- Sphinx Extension which generates various types of diagrams from Verilog code.☆60Updated last year
- Open Source PHY v2☆28Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆30Updated 4 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆6Updated 2 weeks ago
- A compact, configurable RISC-V core☆11Updated 2 months ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- An automatic clock gating utility☆48Updated last month
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆41Updated 2 months ago
- hardware library for hwt (= ipcore repo)☆37Updated last week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week
- ☆32Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- ☆36Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- Drawio => VHDL and Verilog☆55Updated last year