chance189 / I2C_MasterLinks
Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable
☆27Updated 5 years ago
Alternatives and similar repositories for I2C_Master
Users that are interested in I2C_Master are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆70Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 11 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- Asynchronous fifo in verilog☆38Updated 9 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Updated 6 years ago
- ☆40Updated 2 weeks ago
- DDR2 memory controller written in Verilog☆80Updated 13 years ago
- PCIE 5.0 Graduation project (Verification Team)☆100Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆40Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Verilog digital signal processing components☆170Updated 3 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- Verilog RTL Design☆46Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- AXI Interconnect☆56Updated 4 years ago
- UART models for cocotb☆33Updated 5 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆66Updated last year