chance189 / I2C_MasterLinks
Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable
☆21Updated 5 years ago
Alternatives and similar repositories for I2C_Master
Users that are interested in I2C_Master are comparing it to the libraries listed below
Sorting:
- PCIE 5.0 Graduation project (Verification Team)☆85Updated last year
- ☆50Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆55Updated 5 years ago
- Verification IP for APB protocol☆71Updated 4 years ago
- AXI Interconnect☆54Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆66Updated last year
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Structured UVM Course☆51Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- UART design in SV and verification using UVM and SV☆49Updated 5 years ago
- SystemVerilog UVM testbench example☆35Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆71Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆51Updated 5 years ago
- Asynchronous fifo in verilog☆36Updated 9 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- ☆14Updated 3 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆120Updated 3 years ago
- ☆37Updated 5 months ago
- ☆20Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated 2 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆99Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48Updated last year