Alternatives and similar repositories for I2C_Master

Users that are interested in I2C_Master are comparing it to the libraries listed below

• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆52Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆15Updated 10 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆76Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆67Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆42Updated 3 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 2 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆73Updated 4 years ago
• mbits-mirafra / axi4_avip
  ☆37Updated 6 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆47Updated last year
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 3 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆56Updated 5 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆64Updated last year
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆46Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆43Updated 2 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆71Updated 3 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆54Updated 4 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 9 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆161Updated 3 years ago
• mcjtag / axis-uart
  AXI Stream UART (verilog)
  ☆12Updated 6 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆72Updated 4 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆89Updated last year