0xArt / Tiny_But_Mighty_I2C_Master_VerilogLinks
I2C Master Verilog module
☆34Updated 6 months ago
Alternatives and similar repositories for Tiny_But_Mighty_I2C_Master_Verilog
Users that are interested in Tiny_But_Mighty_I2C_Master_Verilog are comparing it to the libraries listed below
Sorting:
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆66Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- Verilog modules required to get the OV7670 camera working☆76Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆74Updated 5 years ago
- Verilog wishbone components☆124Updated last year
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- A series of CORDIC related projects☆120Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆35Updated last year
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆41Updated 2 months ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- IEEE P1735 decryptor for VHDL☆38Updated 10 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆67Updated last year
- A simple DDR3 memory controller☆61Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- UART 16550 core☆37Updated 11 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- Verilog based BCH encoder/decoder☆128Updated 3 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago