0xArt / Tiny_But_Mighty_I2C_Master_VerilogLinks
I2C Master Verilog module
☆34Updated this week
Alternatives and similar repositories for Tiny_But_Mighty_I2C_Master_Verilog
Users that are interested in Tiny_But_Mighty_I2C_Master_Verilog are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆61Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆55Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- IEEE P1735 decryptor for VHDL☆32Updated 9 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆27Updated 11 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Verilog SPI master and slave☆54Updated 9 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆24Updated 2 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆43Updated 3 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Verilog digital signal processing components☆139Updated 2 years ago
- ☆21Updated last month
- UART models for cocotb☆29Updated 2 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- ☆70Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- All digital PLL☆28Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆78Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- ☆15Updated 6 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆37Updated last year