AdriaanSwan / Verilog-I2C-SlaveLinks
Verilog I2C Slave
☆24Updated 11 years ago
Alternatives and similar repositories for Verilog-I2C-Slave
Users that are interested in Verilog-I2C-Slave are comparing it to the libraries listed below
Sorting:
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆40Updated 4 years ago
- Verilog Repository for GIT☆35Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- USB 2.0 Device IP Core☆73Updated 8 years ago
- I2C controller core☆47Updated 3 years ago
- UART models for cocotb☆32Updated 4 months ago
- ☆28Updated 6 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 3 months ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- UART 16550 core☆38Updated 11 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 11 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆14Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆95Updated 3 years ago
- MIPI CSI-2 RX☆37Updated 4 years ago
- ☆33Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated last month
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆16Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Updated 5 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆43Updated 2 years ago