AdriaanSwan / Verilog-I2C-Slave
Verilog I2C Slave
☆23Updated 10 years ago
Alternatives and similar repositories for Verilog-I2C-Slave
Users that are interested in Verilog-I2C-Slave are comparing it to the libraries listed below
Sorting:
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- An i2c master controller implemented in Verilog☆31Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- USB 2.0 Device IP Core☆67Updated 7 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- UART models for cocotb☆29Updated 2 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆37Updated last year
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆23Updated 2 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆26Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- ☆31Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- I2C controller core☆39Updated 2 years ago
- I2C Master and Slave☆33Updated 9 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆15Updated 5 years ago
- USB1.1 Host Controller + PHY☆14Updated 3 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- MIPI CSI-2 RX☆32Updated 3 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago