Alternatives and similar repositories for Verilog-I2C-Slave

Users that are interested in Verilog-I2C-Slave are comparing it to the libraries listed below

• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆35Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆68Updated 4 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆93Updated 3 years ago
• freecores / uart16550
  UART 16550 core
  ☆37Updated 11 years ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆40Updated 4 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 3 months ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆73Updated 8 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 8 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆67Updated 3 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆33Updated 6 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• haifengch / axi_interconnect
  ☆28Updated 5 months ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆24Updated 7 years ago
• shalan / MS_QSPI_XIP_CACHE
  AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
  ☆13Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆12Updated 5 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆62Updated 9 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆18Updated 2 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago
• joelagnel / i2c-master
  An i2c master controller implemented in Verilog
  ☆32Updated 8 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• cudnn / USBtoMIPI
  - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA
  ☆12Updated 8 years ago