AdriaanSwan / Verilog-I2C-SlaveLinks
Verilog I2C Slave
☆23Updated 10 years ago
Alternatives and similar repositories for Verilog-I2C-Slave
Users that are interested in Verilog-I2C-Slave are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆61Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆40Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆85Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆59Updated 4 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- Verilog SPI master and slave☆57Updated 9 years ago
- An i2c master controller implemented in Verilog☆31Updated 8 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- UART 16550 core☆37Updated 11 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆73Updated 2 years ago
- ☆31Updated 5 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆37Updated 4 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- I2C controller core☆47Updated 2 years ago
- UART models for cocotb☆29Updated 2 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆28Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- ☆17Updated 3 weeks ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆15Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆11Updated 8 years ago