Alternatives and similar repositories for Verilog-I2C-Slave:

Users that are interested in Verilog-I2C-Slave are comparing it to the libraries listed below

• joelagnel / i2c-master
  An i2c master controller implemented in Verilog
  ☆32Updated 7 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• makararasi / UVM_AXI4-Stream
  ☆13Updated 2 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆17Updated last year
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆13Updated 10 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated 11 months ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆65Updated 7 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆31Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 5 years ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆32Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆16Updated 5 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 10 months ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆18Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆22Updated 5 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆33Updated 9 years ago
• freecores / uart16550
  UART 16550 core
  ☆33Updated 10 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆19Updated 3 years ago
• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆33Updated last year
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆32Updated 3 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆40Updated 5 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆25Updated 6 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago