jiegec / kbLinks
My knowledge base
☆78Updated this week
Alternatives and similar repositories for kb
Users that are interested in kb are comparing it to the libraries listed below
Sorting:
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- CPU micro benchmarks☆76Updated 3 weeks ago
- Run Rocket Chip on VCU128☆30Updated 3 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Updated last year
- Microarchitecture diagrams of several CPUs☆46Updated last week
- Yet another toy CPU.☆92Updated 2 years ago
- Compile Optimization Guided Binary Translator (using llvm as infrastructure)☆52Updated last year
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Tsinghua Advanced Networking Labs on FPGA☆39Updated last year
- My RV64 CPU (Work in progress)☆19Updated 3 years ago
- ☆23Updated 2 years ago
- CQU Dual Issue Machine☆38Updated last year
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- Documentation for Router Lab☆70Updated 2 months ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Updated 3 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆36Updated 4 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 3 years ago
- nscscc2018☆27Updated 7 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine☆59Updated 2 years ago
- A naive verilog/systemverilog formatter☆21Updated 10 months ago
- Lower chisel memories to SRAM macros☆13Updated last year
- A hand-written recursive decent Verilog parser.☆10Updated last week
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 11 months ago
- RV32I by cats☆15Updated 2 years ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- A Flexible Cache Architectural Simulator☆16Updated 4 months ago