Alternatives and similar repositories for kb

Users that are interested in kb are comparing it to the libraries listed below

• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆76Updated 2 weeks ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆119Updated last year
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated 3 weeks ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆92Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆20Updated 3 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆39Updated last year
• cogbt / COGBT
  Compile Optimization Guided Binary Translator (using llvm as infrastructure)
  ☆52Updated last year
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 3 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆51Updated last month
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆16Updated 4 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 2 months ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆27Updated 7 years ago
• thu-cs-lab / Router-Lab-Docs
  Documentation for Router Lab
  ☆70Updated 2 months ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 11 months ago
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆12Updated 3 years ago
• plctlab / plct-toolbox
  PLCT工具箱
  ☆30Updated 3 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 4 years ago
• t123yh / MIPSCPU
  A simple MIPS CPU for BUAA CO course (and now NSCSCC).
  ☆10Updated 4 years ago
• jiegec / blog-source
  The source of my blog.
  ☆56Updated last week
• CircuitCoder / mill
  RV32I by cats
  ☆15Updated 2 years ago
• dramforever / opensbi-h
  [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆42Updated 5 months ago