jiegec / kb
My knowledge base
☆45Updated this week
Alternatives and similar repositories for kb:
Users that are interested in kb are comparing it to the libraries listed below
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆57Updated 3 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- Tsinghua Advanced Networking Labs on FPGA☆38Updated 4 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆114Updated 4 months ago
- CPU micro benchmarks☆50Updated this week
- Microarchitecture diagrams of several CPUs☆24Updated last month
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆38Updated 7 months ago
- ☆23Updated last year
- Unofficial LoongArch Intrinsics Guide☆42Updated 2 weeks ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine☆54Updated last year
- Project magament for porting openEuler to RISC-V☆34Updated last year
- A Symmetric Multiprocessing OS Kernel over RISC-V☆30Updated 2 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆16Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- Implements kernels with RISC-V Vector☆22Updated last year
- Run Rocket Chip on VCU128☆29Updated 3 months ago
- Lower chisel memories to SRAM macros☆12Updated 11 months ago
- Compile Optimization Guided Binary Translator (using llvm as infrastructure)☆47Updated 7 months ago
- Documentation for Digital Design course☆19Updated 2 weeks ago
- A summarize of my projects.☆47Updated 9 months ago
- Documentation for Router Lab☆67Updated this week
- 项目的主仓库☆23Updated 2 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- National Student Computer System Capability Challenge☆9Updated 6 years ago
- A Flexible Cache Architectural Simulator☆13Updated 3 months ago
- Paging Debug tool for GDB using python☆13Updated 2 years ago