Alternatives and similar repositories for CV

Users that are interested in CV are comparing it to the libraries listed below

• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated 6 months ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆46Updated 2 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• jiegec / Projects
  A summary of my projects
  ☆49Updated 2 months ago
• jiegec / learn_tsinghua_app
  网络学堂 PC 端 App
  ☆21Updated 2 years ago
• Konano / THUCTF2019-Writeups
  THUCTF2019 Writeups
  ☆11Updated 5 years ago
• monkey2000 / LPi4A-Case
  A 3d printed case design for Lichee Pi 4A
  ☆12Updated 2 years ago
• haoxizhong / TUOJ
  Let's discover a new world. — Edit
  ☆10Updated 8 years ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated last year
• vijos / vijosos
  Vijos: Vijos Isn't Just an Operating System
  ☆10Updated 4 years ago
• twd2 / dhop
  Discover Heap OPeration
  ☆9Updated 5 years ago
• LyricZhao / THU-Bell
  THU Bell on macOS
  ☆28Updated 5 years ago
• Konano / Tuna-Erha-Bot
  ☆20Updated 5 months ago
• decaf-lang / minidecaf-tests
  The MiniDecaf test cases.
  ☆17Updated last year
• CircuitCoder / cidr-calc
  CIDR union / subtraction
  ☆14Updated 3 months ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• LyricZhao / ThinRouter
  A SystemVerilog implementation of MIPS32 CPU and RIP router
  ☆23Updated 5 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆21Updated 2 months ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated last month
• MashPlant / lalr1
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆48Updated 3 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆48Updated 4 years ago
• taoky / ayano
  Follow nginx log, and find out bad guys!
  ☆20Updated last month
• skyzh / linux-kernel-labs
  Linux kernel labs
  ☆56Updated 3 years ago
• Cunik / Cunik-engine
  The engine of Cunik.
  ☆26Updated 6 years ago
• z4yx / ucore-thumips
  uCore MIPS32 porting
  ☆18Updated 5 years ago