lijyhh / LEGv8
A simple implementation about LEGv8 instruction set using Verilog HDL.
☆11Updated 3 years ago
Alternatives and similar repositories for LEGv8
Users that are interested in LEGv8 are comparing it to the libraries listed below
Sorting:
- CPU Design Based on RISCV ISA☆107Updated 11 months ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆109Updated last week
- AXI协议规范中文翻译版☆149Updated 2 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆28Updated 2 years ago
- ☆86Updated 2 weeks ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆101Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆49Updated 9 months ago
- An AXI4 crossbar implementation in SystemVerilog☆148Updated this week
- ☆64Updated 2 years ago
- ☆38Updated 4 years ago
- ☆62Updated 9 years ago
- AXI总线连接器☆97Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆159Updated 5 years ago
- Collect some IC textbooks for learning.☆137Updated 2 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- some knowleage about SystemC/TLM etc.☆24Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆85Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆100Updated 2 months ago
- IC Verification & SV Demo☆54Updated 3 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆59Updated 3 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆199Updated 2 years ago
- ☆64Updated 2 years ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆36Updated 4 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆116Updated 12 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- CNN accelerator implemented with Spinal HDL☆149Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago