Alternatives and similar repositories for LEGv8

Users that are interested in LEGv8 are comparing it to the libraries listed below

• ForrestBlue / cortexm0ds
  ☆65Updated 9 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆152Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆114Updated last year
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆99Updated 5 years ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆38Updated 4 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆45Updated 5 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆150Updated last year
• OSCPU / ysyxSoC
  ☆86Updated last month
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• dldldlfma / super_small_toy_tpu
  ☆39Updated 4 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆146Updated 2 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆119Updated last month
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆75Updated 3 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆58Updated 3 years ago
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆29Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆160Updated last week
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆102Updated 4 months ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆51Updated 6 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆45Updated 3 years ago
• lusiyuan-github / ARM_Cortex-M0
  【2022集创赛】Arm杯一等奖作品：Cortex-M0智能娱乐收音机 开源项目
  ☆28Updated 2 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆162Updated 5 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆23Updated 2 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆90Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago