lijyhh / LEGv8Links
A simple implementation about LEGv8 instruction set using Verilog HDL.
☆11Updated 3 years ago
Alternatives and similar repositories for LEGv8
Users that are interested in LEGv8 are comparing it to the libraries listed below
Sorting:
- 【2022集创赛】Arm杯一等奖作品:Cortex-M0智能娱乐收音机 开源项目☆27Updated 2 years ago
- CPU Design Based on RISCV ISA☆123Updated last year
- AXI协议规范中文翻译版☆165Updated 3 years ago
- ☆72Updated 9 years ago
- ☆152Updated last week
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆277Updated 7 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆63Updated last year
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆32Updated 3 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆153Updated 6 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆66Updated 7 years ago
- Collect some IC textbooks for learning.☆172Updated 3 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆209Updated 2 years ago
- ☆89Updated 2 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- AXI总线连接器☆105Updated 5 years ago
- ☆70Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆155Updated last year
- UVM实战随书源码☆56Updated 6 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆121Updated 12 years ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆41Updated 4 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆247Updated 6 years ago
- Implement a bitonic sorting network on FPGA☆46Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆142Updated 6 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆234Updated 2 years ago
- ☆64Updated 3 years ago
- Some useful documents of Synopsys☆90Updated 4 years ago
- ☆45Updated 3 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago