hlslibs / matchlib_connections
Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
☆35Updated 2 weeks ago
Related projects: ⓘ
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆45Updated 4 years ago
- Next generation CGRA generator☆104Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆74Updated 3 weeks ago
- ☆37Updated 4 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆44Updated this week
- For contributions of Chisel IP to the chisel community.☆55Updated 7 months ago
- ☆42Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development