Xilinx / HLS_arbitrary_Precision_TypesLinks
☆46Updated last year
Alternatives and similar repositories for HLS_arbitrary_Precision_Types
Users that are interested in HLS_arbitrary_Precision_Types are comparing it to the libraries listed below
Sorting:
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- ☆30Updated 6 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated last week
- ☆72Updated 2 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated last year
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆45Updated 8 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Algorithmic C Machine Learning Library☆26Updated 7 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- gem5 repository to study chiplet-based systems☆78Updated 6 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆112Updated last month
- ☆24Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- ☆36Updated 4 months ago
- ☆92Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆322Updated 6 months ago