Xilinx / HLS_arbitrary_Precision_Types
☆46Updated last year
Alternatives and similar repositories for HLS_arbitrary_Precision_Types:
Users that are interested in HLS_arbitrary_Precision_Types are comparing it to the libraries listed below
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆29Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- ☆57Updated last year
- Systolic array implementations for Cholesky, LU, and QR decomposition☆41Updated 5 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆51Updated 6 years ago
- ☆23Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆164Updated last year
- ☆90Updated 10 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- ☆71Updated 2 years ago
- SDAccel Development Environment Tutorials☆108Updated 5 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- ☆86Updated last year
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- ☆35Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆122Updated 2 years ago
- ☆57Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆57Updated 2 months ago