Xilinx / HLS_arbitrary_Precision_TypesLinks
☆46Updated last year
Alternatives and similar repositories for HLS_arbitrary_Precision_Types
Users that are interested in HLS_arbitrary_Precision_Types are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆30Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆174Updated last week
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆200Updated 3 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- ☆72Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- ☆24Updated 4 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆114Updated 2 months ago
- ☆36Updated 4 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated 9 months ago
- ☆37Updated 5 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- HLS-based Graph Processing Framework on FPGAs☆148Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- ☆58Updated 5 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- gem5 repository to study chiplet-based systems☆79Updated 6 years ago
- SDAccel Development Environment Tutorials☆110Updated 5 years ago