Xilinx / HLS_arbitrary_Precision_TypesLinks
☆47Updated 2 years ago
Alternatives and similar repositories for HLS_arbitrary_Precision_Types
Users that are interested in HLS_arbitrary_Precision_Types are comparing it to the libraries listed below
Sorting:
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆169Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆177Updated 5 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- ☆72Updated 2 years ago
- ☆39Updated last week
- Tutorials on HLS Design☆52Updated 6 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- ☆30Updated 6 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- A DSL for Systolic Arrays☆83Updated 7 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆24Updated 5 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆118Updated 7 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆47Updated last year
- SDAccel Development Environment Tutorials☆109Updated 5 years ago
- ☆36Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago