Xilinx / HLS_arbitrary_Precision_Types
☆46Updated 11 months ago
Related projects ⓘ
Alternatives and complementary repositories for HLS_arbitrary_Precision_Types
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture☆124Updated 2 weeks ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆156Updated this week
- Tutorials on HLS Design☆49Updated 4 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆40Updated last week
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- ☆23Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆71Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- ☆87Updated 8 months ago
- ☆27Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- FPGA version of Rodinia in HLS C/C++☆31Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- ☆57Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆59Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- ☆17Updated 3 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆158Updated last year
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆192Updated 3 years ago
- ☆83Updated 5 months ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- ☆70Updated last year
- HLS-based Graph Processing Framework on FPGAs☆139Updated 2 years ago