CAN Protocol Controller
☆43Jul 17, 2014Updated 12 years ago
Alternatives and similar repositories for can
Users that are interested in can are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An CAN bus Controller implemented in Verilog☆56May 28, 2015Updated 11 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆18Apr 17, 2021Updated 5 years ago
- SpaceWire☆14Jul 17, 2014Updated 12 years ago
- Open Source Cell Library for Predictive CNFET Technology☆15Mar 12, 2026Updated 4 months ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- I2C controller core☆53Jan 1, 2023Updated 3 years ago
- matlab code of ldpc☆15Oct 25, 2016Updated 9 years ago
- Repo is used to store Doxygen documentation for BM drivers☆23Jun 24, 2026Updated last month
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆22Jul 17, 2014Updated 12 years ago
- SPI core☆12Jul 17, 2014Updated 12 years ago
- STM32 Embedded Modules☆20Jul 30, 2025Updated 11 months ago
- Freecores website☆19Dec 22, 2016Updated 9 years ago
- VHDL plugin for RgGen☆15Jul 1, 2026Updated 3 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Amber ARM-compatible core☆18Jul 17, 2014Updated 12 years ago
- few python scripts to clone all IP cores from opencores.org☆29Jan 8, 2024Updated 2 years ago
- RISC-V by VectorBlox☆12Jul 19, 2017Updated 9 years ago
- A lightweight Controller Area Network (CAN) controller in VHDL☆31Oct 30, 2024Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- Modulation and Arbitrary Waveform Generator☆20Feb 16, 2021Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- SpaceWire Light☆19Jul 17, 2014Updated 12 years ago
- ☆19Feb 24, 2026Updated 5 months ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- LZW压缩算法的完整实现☆10Aug 14, 2014Updated 11 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- Gaussian noise generator Verilog IP core☆34Jul 5, 2026Updated 3 weeks ago
- PID controller☆25Jul 17, 2014Updated 12 years ago
- 补充了一些Visualglm缺少的文件,可以对Visualglm进行训练,实例中是对人脸做了面相的识别☆13Jun 7, 2023Updated 3 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Self-driving Model Car with RPi☆10Nov 27, 2020Updated 5 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Source code of basic Xilinx Vivado HLS image processing tutorial using HLS openCV functions☆26Jul 7, 2018Updated 8 years ago
- HDMI Audio/Video signal generation for HW emulators of retro comuters☆12Mar 23, 2016Updated 10 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- ☆38Jul 11, 2022Updated 4 years ago