CAN Protocol Controller
☆43Jul 17, 2014Updated 12 years ago
Alternatives and similar repositories for can
Users that are interested in can are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An CAN bus Controller implemented in Verilog☆56May 28, 2015Updated 11 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆19Apr 17, 2021Updated 5 years ago
- SpaceWire☆14Jul 17, 2014Updated 12 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- I2C controller core☆53Jan 1, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- matlab code of ldpc☆15Oct 25, 2016Updated 9 years ago
- UART 16550 core☆42Jul 17, 2014Updated 12 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- SPI core☆12Jul 17, 2014Updated 12 years ago
- STM32 Embedded Modules☆21Jul 30, 2025Updated last year
- VHDL plugin for RgGen☆15Jul 1, 2026Updated last month
- Freecores website☆19Dec 22, 2016Updated 9 years ago
- Amber ARM-compatible core☆18Jul 17, 2014Updated 12 years ago
- AD9363 + XC6SLX9 board☆12Apr 23, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- VLSI placement and routing tool☆15Dec 20, 2025Updated 7 months ago
- A lightweight Controller Area Network (CAN) controller in VHDL☆31Oct 30, 2024Updated last year
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- Modulation and Arbitrary Waveform Generator☆20Feb 16, 2021Updated 5 years ago
- SpaceWire Light☆20Jul 17, 2014Updated 12 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- LZW压缩算法的完整实现☆10Aug 14, 2014Updated 12 years ago
- SixtySecondsCV☆16Jul 23, 2020Updated 6 years ago
- PID controller☆25Jul 17, 2014Updated 12 years ago
- Fork of github.com/UCSBarchlab/OpenTPU for the TGPTPU project☆15Jun 1, 2025Updated last year
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- HDMI Audio/Video signal generation for HW emulators of retro comuters☆12Mar 23, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- ☆39Jul 11, 2022Updated 4 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- A Verilog parser for Haskell.☆37Jul 6, 2021Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- Qt QML source code for Raspberry Motorized Cam project☆22Jan 10, 2021Updated 5 years ago
- ARM-CPU implemented verilog☆30Jan 13, 2024Updated 2 years ago