Alternatives and similar repositories for uart_dpi

Users that are interested in uart_dpi are comparing it to the libraries listed below

• schoeberl / wildcat
  An implementation of RISC-V
  ☆32Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆99Updated 2 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆52Updated 3 weeks ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆84Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆57Updated 2 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated 7 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆56Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆52Updated 5 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• pieter3d / simview
  ☆78Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆56Updated last week
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆106Updated this week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆57Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• verilator / example-systemverilog
  ☆38Updated last year
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 5 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆46Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last month
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆63Updated 11 months ago