Alternatives and similar repositories for uart_dpi

Users that are interested in uart_dpi are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆153Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆74Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated last year
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆101Updated last month
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆164Updated last week
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• schoeberl / wildcat
  An implementation of RISC-V
  ☆42Updated 2 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆107Updated last month
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated this week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆147Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆182Updated 2 weeks ago
• pieter3d / simview
  ☆85Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆212Updated 7 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆88Updated 2 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆54Updated 6 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆113Updated 4 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated 4 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• yne / vcd
  VCD file (Value Change Dump) command line viewer
  ☆120Updated 2 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 11 months ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆87Updated last year