rdiez / uart_dpiLinks
DPI module for UART-based console interaction with Verilator simulations
☆25Updated 12 years ago
Alternatives and similar repositories for uart_dpi
Users that are interested in uart_dpi are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated 2 months ago
- ☆80Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 6 months ago
- An implementation of RISC-V☆43Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Yet Another RISC-V Implementation☆97Updated last year
- RISC-V Formal Verification Framework☆150Updated this week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆178Updated this week
- Naive Educational RISC V processor☆88Updated 2 months ago
- FuseSoC standard core library☆147Updated 3 months ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- SystemVerilog frontend for Yosys☆161Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last month
- Demo SoC for SiliconCompiler.☆61Updated this week
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- ☆52Updated 5 months ago
- RISC-V Nox core☆68Updated 2 months ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 8 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆122Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- ☆40Updated last year
- WAL enables programmable waveform analysis.☆155Updated 3 months ago
- SystemVerilog synthesis tool☆209Updated 6 months ago
- Visual Simulation of Register Transfer Logic☆101Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year