Alternatives and similar repositories for LimeSDR-PCIe_GW:

Users that are interested in LimeSDR-PCIe_GW are comparing it to the libraries listed below

• myriadrf / LimeSDR-PCIe
  ☆34Updated 7 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last week
• FDU-ME-ARC / NVMeCHA
  ☆14Updated 3 years ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆26Updated last month
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆19Updated 6 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• ianhchuang / EPC-Gen2-RFID-Tag-Baseband-Processor
  Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers
  ☆29Updated 3 years ago
• myriadrf / FreeSRP_GW
  The FPGA design for the FreeSRP's Artix 7 FPGA
  ☆23Updated 7 years ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆15Updated 10 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• ymz000 / Kintex-7-xc7k325-pcb
  基于Kintex-7 XC7K325T的高性能FPGA功能验证板
  ☆19Updated 4 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆12Updated 6 years ago
• JacekGreniger / fpga-sdr-platform
  FPGA SDR platform: AD9963 + XC6SLX9 + CY7C68013
  ☆15Updated 11 years ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆31Updated 9 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• pothosware / PothosZynq
  DMA source and sink blocks for Xilinx Zynq FPGAs
  ☆22Updated 4 years ago
• bitflippersanonymous / fpga-camera
  FPGA digital camera controller and frame capture device in VHDL
  ☆15Updated 11 years ago
• myriadrf / STREAM
  FPGA development platform for high-performance RF and digital design
  ☆32Updated 9 years ago
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆19Updated 5 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• dawsonjon / Chips-Demo
  Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
  ☆14Updated 7 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• circuitvalley / USB3_MIPI_CSI2_RX_V2_Crosslink_NX
  MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…
  ☆48Updated 4 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆33Updated last year
• takeshineshiro / fpga_fibre_scan
  本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取…
  ☆25Updated 9 years ago
• FeldmeierMichael / MIPI_CSI_2
  ☆13Updated last year
• aomtoku / hdmi-ts
  hdmi-ts Project
  ☆13Updated 7 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago