Alternatives and similar repositories for my_vimrc

Users that are interested in my_vimrc are comparing it to the libraries listed below

• hjking / uvm_gen
  UVM Generator
  ☆46Updated last year
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆69Updated 5 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆43Updated 3 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆33Updated 5 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆37Updated last year
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆55Updated 8 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆74Updated 4 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆23Updated 6 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆50Updated 10 years ago
• troyguo / dvcon_download
  Download proccedings from DVCon
  ☆22Updated 4 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆86Updated 7 months ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆40Updated 5 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆40Updated last year
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆41Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆67Updated 4 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆76Updated 3 years ago
• shady831213 / jarvisuk
  Just A Really Very Impressive Systemverilog UVM Kit
  ☆18Updated 4 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 4 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆140Updated 4 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆35Updated 3 years ago
• zhajio1988 / uvm_candy_lover
  UVM candy lover testbench which uses YASA as simulation script
  ☆17Updated 5 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆52Updated 6 years ago
• Juniper / simple_reg_model
  System verilog register model for uvm testbenches.
  ☆19Updated 6 years ago
• freecores / apbi2c
  APB to I2C
  ☆42Updated 11 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆105Updated 3 years ago