zhajio1988 / my_vimrcLinks
Jude's vimrc for DV work(fine tuning for SV/UVM)
☆19Updated last year
Alternatives and similar repositories for my_vimrc
Users that are interested in my_vimrc are comparing it to the libraries listed below
Sorting:
- UVM Generator☆47Updated last year
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆70Updated 5 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆56Updated 8 years ago
- ☆43Updated last year
- Yet Another Simulation Architecture☆76Updated 5 years ago
- JSON lib in Systemverilog☆44Updated 3 years ago
- amba3 apb/axi vip☆51Updated 10 years ago
- generate UVM testbench using python☆28Updated 7 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- ☆14Updated last year
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- UVM register utility generation by inputting xls table☆39Updated 2 years ago
- UART design in SV and verification using UVM and SV☆49Updated 5 years ago
- This is the repository for the IEEE version of the book☆74Updated 5 years ago
- uvm auto generator☆24Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Download proccedings from DVCon☆22Updated 4 years ago
- Sample UVM code for axi ram dut☆37Updated 3 years ago
- UVM AHB VIP☆87Updated last month
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Updated 5 years ago
- Verification IP for APB protocol☆71Updated 4 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆32Updated 5 years ago
- UVM agents☆83Updated 8 years ago
- SystemVerilog VIP for AMBA APB protocol☆79Updated 3 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆46Updated 5 years ago
- Novel GUI Based UVM Testbench Template Builder☆144Updated 4 years ago
- UVM verification kits which uses YASA as simulation script☆15Updated 5 years ago
- UVM Verification IP to uart2bus IP.☆23Updated 3 years ago