zhajio1988 / my_vimrcLinks
Jude's vimrc for DV work(fine tuning for SV/UVM)
☆20Updated last year
Alternatives and similar repositories for my_vimrc
Users that are interested in my_vimrc are comparing it to the libraries listed below
Sorting:
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 6 years ago
- UVM Generator☆47Updated last year
- Yet Another Simulation Architecture☆77Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆31Updated 5 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆56Updated 8 years ago
- amba3 apb/axi vip☆51Updated 10 years ago
- uvm auto generator☆24Updated 7 years ago
- JSON lib in Systemverilog☆44Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 2 years ago
- UVM verification kits which uses YASA as simulation script☆17Updated 5 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- ☆44Updated 2 years ago
- ☆14Updated last year
- UVM register utility generation by inputting xls table☆39Updated 2 years ago
- UART design in SV and verification using UVM and SV☆50Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆51Updated last week
- Sample UVM code for axi ram dut☆37Updated 3 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆69Updated last year
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆32Updated 5 years ago
- The source code of blog☆14Updated 3 years ago
- UVM VIP architecture generator☆20Updated 5 years ago
- This is the repository for the IEEE version of the book☆75Updated 5 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- Download proccedings from DVCon☆22Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆57Updated 5 years ago
- Customized UVM Report Server☆41Updated 5 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- generate UVM testbench using python☆28Updated 7 years ago