zhajio1988 / my_vimrc
Jude's vimrc for DV work(fine tuning for SV/UVM)
☆18Updated last year
Alternatives and similar repositories for my_vimrc:
Users that are interested in my_vimrc are comparing it to the libraries listed below
- UVM Generator☆45Updated 11 months ago
- DOULOS Easier UVM Code Generator☆33Updated 7 years ago
- generate UVM testbench using python☆27Updated 7 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 8 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- ☆40Updated last year
- System verilog register model for uvm testbenches.☆19Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆34Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- uvm auto generator☆23Updated 6 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆32Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- Download proccedings from DVCon☆22Updated 3 years ago
- UVM register utility generation by inputting xls table☆36Updated last year
- UVM candy lover testbench which uses YASA as simulation script☆16Updated 5 years ago
- ☆21Updated 3 years ago
- JSON lib in Systemverilog☆43Updated 3 years ago
- amba3 apb/axi vip☆47Updated 10 years ago
- Customized UVM Report Server☆40Updated 5 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆15Updated last year
- UVM VIP architecture generator☆19Updated 4 years ago
- This is the repository for the IEEE version of the book☆58Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆54Updated last year
- ☆25Updated 3 years ago
- soc integration script and integration smoke script☆22Updated 2 years ago
- UVM Clock and Reset Agent☆13Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- Yet Another Simulation Architecture☆72Updated 4 years ago