Jude's vimrc for DV work(fine tuning for SV/UVM)
☆21Mar 12, 2024Updated 2 years ago
Alternatives and similar repositories for my_vimrc
Users that are interested in my_vimrc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- UVM candy lover testbench which uses YASA as simulation script☆17Apr 17, 2020Updated 5 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆46Aug 31, 2025Updated 6 months ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jan 7, 2026Updated 2 months ago
- Source code repo for UVM Tutorial for Candy Lovers☆14Apr 23, 2017Updated 8 years ago
- Yet Another Simulation Architecture☆79Sep 17, 2020Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- System on Chip verified with UVM/OSVVM/FV☆34Feb 28, 2026Updated last month
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- UVM verification kits which uses YASA as simulation script☆17Dec 10, 2019Updated 6 years ago
- SystemVerilog syntax highlight/indent support in vim☆52Jul 10, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- ☆11May 31, 2016Updated 9 years ago
- Novel GUI Based UVM Testbench Template Builder☆151Apr 14, 2021Updated 4 years ago
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆116Nov 27, 2017Updated 8 years ago
- Describes the best coding practices and guidelines☆11Jan 4, 2024Updated 2 years ago
- highlighting match of matchit.vim☆18May 4, 2014Updated 11 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Nov 29, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆16Jun 13, 2025Updated 9 months ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- Coresight Wire Protocol (CSWP) Server/Client and streaming trace examples.☆28Jul 10, 2025Updated 8 months ago
- HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and aut…☆36Oct 28, 2024Updated last year
- UVM实战随书源码☆60Jan 22, 2019Updated 7 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Oct 26, 2019Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 5 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆162Jul 16, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- This is for uvm_tb_gen☆52Feb 13, 2025Updated last year
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Medium Access Control layer of 802.15.4☆12Nov 14, 2014Updated 11 years ago
- svlib from http://www.verilab.com/resources/svlib/☆24Jun 2, 2020Updated 5 years ago
- ☆11Apr 15, 2024Updated last year
- C++软件开发工程师面试学习笔记☆12Oct 2, 2020Updated 5 years ago