Alternatives and similar repositories for cheri-exercises

Users that are interested in cheri-exercises are comparing it to the libraries listed below

• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆59Updated last week
• CTSRD-CHERI / cheribuild
  Easily build and run CHERI related projects
  ☆77Updated this week
• CTSRD-CHERI / cheri-specification
  CHERI ISA Specification
  ☆24Updated last year
• CTSRD-CHERI / llvm-project
  Fork of LLVM adding CHERI support
  ☆56Updated this week
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆131Updated 11 months ago
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆23Updated 5 years ago
• CPU-THU / Spectre-V4-ng
  The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…
  ☆22Updated last year
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆69Updated 4 months ago
• hrosier / ripe64
  64-bit port of the RIPE benchmark (buffer overflow attacks). RIPE was originally developed by John Wilander and Nick Nikiforakis and pres…
  ☆22Updated 3 years ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆30Updated 3 weeks ago
• FxPiGaAo / Hacky-Racer
  ☆16Updated last month
• vusec / tlbdr
  ☆18Updated 2 years ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆92Updated 3 weeks ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆120Updated 2 months ago
• lsds / intravisor
  Virtualisation platform using CHERI for isolation and sharing
  ☆39Updated last year
• embecosm / mibench
  The MiBench testsuite, extended for use in general embedded environments
  ☆101Updated 12 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated last month
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆20Updated this week
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 3 years ago
• bu-icsg / PHMon
  This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).
  ☆26Updated 5 years ago
• kvm-unit-tests / kvm-unit-tests
  This is a read-only mirror of the kvm-unit-tests repository from https://gitlab.com/kvm-unit-tests/kvm-unit-tests. Pull requests here at …
  ☆28Updated 2 weeks ago
• flowyroll / uarchsec
  ☆45Updated 6 years ago
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆24Updated last month
• ARM-software / data
  Machine-readable data describing Arm architecture and implementations. Includes JSON descriptions of implemented PMU events.
  ☆54Updated 6 months ago
• compsec-snu / difuzz-rtl
  ☆92Updated last year