CTSRD-CHERI / cheri-exercisesLinks
Learning exercises for CHERI
☆20Updated 2 months ago
Alternatives and similar repositories for cheri-exercises
Users that are interested in cheri-exercises are comparing it to the libraries listed below
Sorting:
- QEMU with support for CHERI☆59Updated this week
- Easily build and run CHERI related projects☆80Updated last week
- RISC-V Security Model☆32Updated last week
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- ☆16Updated 9 months ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆70Updated 6 months ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆135Updated last year
- CHERI ISA Specification☆24Updated last month
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆92Updated last week
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- ☆18Updated 3 years ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Updated last year
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆22Updated last year
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆65Updated 5 years ago
- Fork of LLVM adding CHERI support☆57Updated last week
- ☆95Updated last year
- Risc-V hypervisor for TEE development☆122Updated 3 months ago
- ☆17Updated 3 months ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆23Updated last year
- HW interface for memory caches☆28Updated 5 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆40Updated last year
- Security Test Benchmark for Computer Architectures☆21Updated this week
- ☆21Updated 5 months ago
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆21Updated last month
- rfuzz: coverage-directed fuzzing for RTL research platform☆111Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆26Updated 3 months ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆25Updated 2 months ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆22Updated 2 weeks ago