Alternatives and similar repositories for libaji_client:

Users that are interested in libaji_client are comparing it to the libraries listed below

• intel / aji_openocd
  A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the A…
  ☆12Updated 8 months ago
• BLangOS / VexRiscV_with_HW-GDB_Server
  VexRiscV system with GDB-Server in Hardware
  ☆20Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆29Updated 4 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆16Updated 3 years ago
• azonenberg / jtaghal
  JTAG Hardware Abstraction Library
  ☆36Updated last year
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆53Updated 2 years ago
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• tomverbeure / sidechan
  Side channel communication test within an FPGA
  ☆11Updated 4 years ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆52Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆28Updated 4 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆43Updated this week
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated last week
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆17Updated last year
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 3 weeks ago
• FPGA-Research / FPGAVirusScanner
  Program to scan for malicious FPGA designs.
  ☆14Updated 4 years ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• airbus-seclab / sdmmc-analyzer
  SD/MMC Analyzer for Saleae Logic
  ☆37Updated last year
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 7 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆29Updated last year
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 3 weeks ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago