Alternatives and similar repositories for libaji_client

Users that are interested in libaji_client are comparing it to the libraries listed below

• intel / aji_openocd
  A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the A…
  ☆12Updated 10 months ago
• BLangOS / VexRiscV_with_HW-GDB_Server
  VexRiscV system with GDB-Server in Hardware
  ☆21Updated 2 years ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆57Updated 5 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Updated 3 years ago
• jevinskie / liteluna
  LiteX LUNA USB stack integration
  ☆14Updated 3 years ago
• tomverbeure / sidechan
  Side channel communication test within an FPGA
  ☆11Updated 4 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆19Updated last year
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆48Updated 3 weeks ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆28Updated 4 years ago
• FPGA-Research / FPGAVirusScanner
  Program to scan for malicious FPGA designs.
  ☆14Updated 4 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆29Updated 5 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 5 months ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆50Updated 7 years ago
• azonenberg / jtaghal
  JTAG Hardware Abstraction Library
  ☆36Updated last year
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago
• wd5gnr / verifla
  Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
  ☆33Updated 6 years ago
• jevinskie / litespih4x
  SPI flash MITM and emulation (QSPI is a WIP)
  ☆20Updated 3 years ago
• amaranth-lang / amaranth-stdio
  Industry standard I/O for Amaranth HDL
  ☆28Updated 9 months ago
• swetland / os-workshop
  Some materials and sample source for RV32 OS projects.
  ☆22Updated 3 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 3 months ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆55Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆40Updated last year
• shacron / sled
  Sled System Emulator
  ☆28Updated 2 months ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago