ReconOS / reconos
ReconOS - Operating System for Reconfigurable Hardware
☆29Updated 2 years ago
Alternatives and similar repositories for reconos:
Users that are interested in reconos are comparing it to the libraries listed below
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ☆84Updated 2 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Open Processor Architecture☆26Updated 8 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 6 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆94Updated 5 years ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- SoCRocket - Core Repository☆34Updated 7 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆54Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Xilinx Unisim Library in Verilog☆72Updated 4 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- A Verilog Synthesis Regression Test☆35Updated 9 months ago
- Extensible FPGA control platform☆55Updated last year
- ☆23Updated 8 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆47Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 3 months ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆98Updated 5 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆37Updated 4 months ago
- Documentation for the BOOM processor☆47Updated 7 years ago
- SoftCPU/SoC engine-V☆54Updated last year