ReconOS - Operating System for Reconfigurable Hardware
☆29Feb 4, 2022Updated 4 years ago
Alternatives and similar repositories for reconos
Users that are interested in reconos are comparing it to the libraries listed below
Sorting:
- Yosys Plugins☆22Jul 16, 2019Updated 6 years ago
- ☆27Feb 15, 2025Updated last year
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 5 years ago
- "mmult" example using SDSoC for PYNQ board☆11Feb 23, 2017Updated 9 years ago
- ☆16Aug 21, 2019Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Sep 3, 2021Updated 4 years ago
- Zynq PR Management☆13Apr 20, 2016Updated 9 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆18Nov 15, 2019Updated 6 years ago
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Jul 11, 2016Updated 9 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 7 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- ☆16Feb 5, 2021Updated 5 years ago
- ☆25Mar 27, 2020Updated 5 years ago
- A utility for Composing FPGA designs from Peripherals☆186Dec 23, 2024Updated last year
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆22Dec 17, 2015Updated 10 years ago
- Scripts to create a boot.bin file for linux on Xilinx Zync☆26Jun 3, 2016Updated 9 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- FPGA development in PlatformIO, using the Icestorm opensource toolchain☆21Oct 22, 2016Updated 9 years ago
- A simulator of a memory controller designed for hybrid DRAM+NVM.☆22Dec 28, 2015Updated 10 years ago
- PCBNEW plugin that highlights pads on a PCB that meet specified criteria (part, unit, number, name, and function).☆25Sep 17, 2021Updated 4 years ago
- Virtual Development Board☆64Nov 26, 2021Updated 4 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆56Apr 27, 2017Updated 8 years ago
- A mixed signal netlist language (pre-alpha)☆61Aug 20, 2018Updated 7 years ago
- SpinalHDL - Cryptography libraries☆59Jul 19, 2024Updated last year
- Small footprint and configurable Inter-Chip communication cores☆66Feb 20, 2026Updated last week
- soap - Structural Optimisation of Arithmetic Programs☆24May 9, 2016Updated 9 years ago
- mystorm sram test☆29Sep 12, 2017Updated 8 years ago
- The code for both the framework and experiments from the NSDI '19 paper "Loom: Flexible and Efficient NIC Packet Scheduling"☆31Feb 4, 2019Updated 7 years ago
- FGPU is a soft GPU architecture general purpose computing☆61Nov 9, 2020Updated 5 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Feb 13, 2026Updated 2 weeks ago
- ☆21Jul 28, 2016Updated 9 years ago
- a wavelet-based multifractal image analysis tool implementing the WTMM (Wavelet Transform Modulus Maxima) method.☆11Feb 1, 2020Updated 6 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 4 years ago
- ☆23Feb 23, 2016Updated 10 years ago