Alternatives and similar repositories for Alveo_Chinese:

Users that are interested in Alveo_Chinese are comparing it to the libraries listed below

• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆69Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• synergy-noc-generators / Proteus
  ☆9Updated 2 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆23Updated 7 months ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆48Updated 3 weeks ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 7 months ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆130Updated last month
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆13Updated 8 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• awai54st / LUTNet
  ☆57Updated 4 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• DSDL-EE / PYNQ-ZU_Tutorial
  ☆12Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆46Updated 5 months ago
• VeriGOOD-ML / public
  ☆57Updated last year
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆12Updated 4 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆35Updated 3 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆47Updated this week
• valar1234 / SDAI
  An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool
  ☆15Updated 8 years ago
• sharc-lab / FPGA_ECE8893
  ☆33Updated this week
• GramThanos / CPU-on-Vivado-HLS
  A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
  ☆18Updated 5 years ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated last year
• groupsada / DeepBurning
  Automatic generation of FPGA-based learning accelerators for the neural network family
  ☆62Updated 5 years ago
• maestro-project / gamma
  ☆39Updated 8 months ago