xupsh / Alveo_ChineseLinks
Chinese Guide for Alveo Getting Started
☆12Updated 5 years ago
Alternatives and similar repositories for Alveo_Chinese
Users that are interested in Alveo_Chinese are comparing it to the libraries listed below
Sorting:
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- ☆72Updated 2 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆96Updated last year
- ☆24Updated 4 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- ☆71Updated 6 years ago
- Verilog implementation of Softmax function☆76Updated 3 years ago
- ☆19Updated 6 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 5 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆34Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆163Updated this week
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆70Updated 3 weeks ago
- eyeriss-chisel3☆40Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 2 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- ☆20Updated last year
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆67Updated 3 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- An integrated CGRA design framework☆91Updated 8 months ago