xupsh / Alveo_ChineseLinks
Chinese Guide for Alveo Getting Started
☆12Updated 5 years ago
Alternatives and similar repositories for Alveo_Chinese
Users that are interested in Alveo_Chinese are comparing it to the libraries listed below
Sorting:
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- RTL implementation of Flex-DPE.☆108Updated 5 years ago
- ☆72Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- ☆17Updated 2 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆148Updated this week
- ☆36Updated 4 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 6 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆71Updated 5 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- ☆31Updated 2 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆65Updated 6 years ago
- ☆24Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆57Updated 4 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- Open-source of MSD framework☆16Updated last year
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago