Real-time Audio Processing through FIR filters on Basys-3 FPGA and Pmod I2S2
☆13Feb 1, 2023Updated 3 years ago
Alternatives and similar repositories for fir_basys3
Users that are interested in fir_basys3 are comparing it to the libraries listed below
Sorting:
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- FIR and LMS filter implementations in FPGAs☆14Nov 18, 2019Updated 6 years ago
- ☆12Nov 3, 2022Updated 3 years ago
- LTspice libraries for Würth Elektronik products☆16Updated this week
- Optimize the construction of earthquake-resistant buildings☆10Jul 7, 2024Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- This source code (in Python) is a preliminary implementation of my quadratic-time positive integer matrix multiplication.☆10Nov 23, 2022Updated 3 years ago
- ☆10Feb 13, 2021Updated 5 years ago
- Python scripts that build optimal routes for node collection☆12Feb 26, 2026Updated last week
- SNN implementation of the Fourier transform in neuromorphic hardware☆10Mar 7, 2022Updated 3 years ago
- USB audio device☆12Feb 9, 2021Updated 5 years ago
- C subset compiler written in ruby.☆12Oct 6, 2021Updated 4 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 2 years ago
- DSP by FPGA☆15Sep 12, 2023Updated 2 years ago
- Learning FPGA, yosys, nextpnr, and RISC-V☆13Jan 5, 2021Updated 5 years ago
- This repository has basic examples in VHDL using Basys3 board.☆13Aug 15, 2020Updated 5 years ago
- Timeline Widget for the Amazfit Pace / Stratos☆14Nov 20, 2019Updated 6 years ago
- Repository to replicate the Enigma Machine and the Turing-Welchman Bombe☆12Jun 19, 2019Updated 6 years ago
- Python programming for Digital Signal Processing algorithm implementations☆11Dec 26, 2022Updated 3 years ago
- An explanation of patents from Neuralink in PPT format (some including Python Jupyter notebooks). For educational purposes only.☆15Nov 26, 2024Updated last year
- 16-Point FFT is developed in order to accurately model that of the MATLAB function. . The module successfully tested using verilog testbe…☆18May 27, 2016Updated 9 years ago
- Projects using the Sipeed Tang Primer FPGA development board☆16Dec 6, 2020Updated 5 years ago
- Chromium extensions for LeetCode Fixes.☆17Feb 17, 2026Updated 2 weeks ago
- USB Audio Interface☆16Feb 13, 2022Updated 4 years ago
- An SPDIF Hat for the Raspberry Pi 2-X for SPDIF Communication☆18Aug 28, 2022Updated 3 years ago
- Source code for photolithography stepper software☆22Feb 26, 2026Updated last week
- Cordic fixed point math☆21Jul 17, 2024Updated last year
- Python client library and command line utility for interacting with Synapse devices☆19Feb 11, 2026Updated 3 weeks ago
- USB audio interface,design by STM32 and EP4CE6 FPGA,support DSD☆15Jan 20, 2017Updated 9 years ago
- Vita Dao Smart Contracts☆17Jan 24, 2023Updated 3 years ago
- verilog example to drive PCM5102 DAC with FPGA☆18Apr 30, 2018Updated 7 years ago
- A tiny agent.☆43Updated this week
- ☆18Jul 17, 2020Updated 5 years ago
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆22Feb 28, 2022Updated 4 years ago
- BlueMuse Alternative with MATLAB Stream (UDP)☆15Sep 12, 2025Updated 5 months ago
- FT2232HL JTAG & UART Downloader☆20Jul 18, 2021Updated 4 years ago
- A loader to bypass firmware flashing authentication on cloned Amanero Combo384 USB card☆16Dec 14, 2022Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆78Apr 11, 2022Updated 3 years ago