Alternatives and similar repositories for pygmyhdl

Users that are interested in pygmyhdl are comparing it to the libraries listed below

• PyLCARS / PythonUberHDL
  Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
  ☆36Updated 7 years ago
• jck / uhdl
  Utilities for MyHDL
  ☆19Updated 2 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• devbisme / myhdlpeek
  Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
  ☆40Updated last year
• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆21Updated 10 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• cfelton / rhea
  A collection of MyHDL cores and tools for complex digital circuit design
  ☆86Updated 7 years ago
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆24Updated 4 years ago
• carlos-jenkins / csv2vcd
  Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.
  ☆11Updated 4 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago
• quartiq / redpid
  migen + misoc + redpitaya = digital servo
  ☆41Updated 7 years ago
• andrecp / myhdl_simple_uart
  A very simple UART implementation in MyHDL
  ☆17Updated 11 years ago
• EvgenyMuryshkin / QuokkaEvaluation
  Example projects for Quokka FPGA toolkit
  ☆37Updated 3 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆48Updated 5 years ago
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆19Updated 8 years ago
• UGent-HES / tlut_flow
  TLUT tool flow for parameterised configurations for FPGAs
  ☆16Updated last year
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• Digilent / SDSoC-platforms
  SDSoC platforms for Digilent Zynq boards
  ☆12Updated 8 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆19Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated this week
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 5 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆40Updated last month
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• ggventurini / python-deltasigma
  A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep
  ☆94Updated 3 years ago