RohanNagar / parallel-logic-networksLinks
Gate-Level Simulation on a GPU
☆10Updated 9 years ago
Alternatives and similar repositories for parallel-logic-networks
Users that are interested in parallel-logic-networks are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- IRSIM switch-level simulator for digital circuits☆35Updated last month
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆26Updated last month
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- EDA wiki☆53Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆20Updated last year
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Updated 10 months ago
- Visual Simulation of Register Transfer Logic☆109Updated 4 months ago
- The PE for the second generation CGRA (garnet).☆17Updated 8 months ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- Convert C files into Verilog☆19Updated 6 years ago
- mantle library☆44Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Updated 9 years ago
- Mutation Cover with Yosys (MCY)☆89Updated last month
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- An advanced header-only exact synthesis library☆30Updated 3 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 9 months ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- ☆33Updated 3 years ago
- Collection of test cases for Yosys☆17Updated 4 years ago