Alternatives and similar repositories for qATG

Users that are interested in qATG are comparing it to the libraries listed below

• NTU-ALComLab / LSV-PA
  Logic Synthesis and Verification: Programming Assignments
  ☆13Updated last week
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆31Updated last year
• daitoto / EDA-wiki
  EDA wiki
  ☆53Updated 2 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆28Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• mflowgen / skywater-130nm
  ASIC Design kit for Skywater 130 for use with mflowgen
  ☆13Updated 2 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆96Updated 3 months ago
• twweeb / VLSI-Physical-Design-Automation
  Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
  ☆48Updated 4 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆198Updated last year
• lsils / kitty
  C++ truth table library
  ☆61Updated 2 months ago
• vsdip / avsddac_3v3_sky130_v2
  ☆17Updated 3 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• najaeda / naja-verilog
  A standalone structural (gate-level) verilog parser
  ☆39Updated last month
• limbo018 / OpenMPL
  An open multiple patterning framework
  ☆79Updated last year
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆142Updated last month
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆14Updated 8 years ago
• marcelwa / aigverse
  A Python library for working with logic networks, synthesis, and optimization.
  ☆65Updated this week
• lsils / mockturtle
  C++ logic network library
  ☆255Updated 2 weeks ago
• nbulsi / also
  A logic synthesis tool
  ☆82Updated last month
• pulp-platform / ELAU
  ☆19Updated last year
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆15Updated last year
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆32Updated 6 years ago
• eisl-nctu / aquila
  Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.
  ☆34Updated last year
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 6 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆58Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆103Updated last month
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆51Updated 2 years ago