seongsikpark / MANN-FPGALinks
Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)
☆12Updated 4 years ago
Alternatives and similar repositories for MANN-FPGA
Users that are interested in MANN-FPGA are comparing it to the libraries listed below
Sorting:
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆23Updated 3 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆34Updated 7 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆60Updated 2 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- ☆25Updated 3 years ago
- The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"☆11Updated last year
- sram/rram/mram.. compiler☆37Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- CNN accelerator☆27Updated 8 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- Physical memristor/RRAM/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices sett…☆45Updated 5 years ago
- System Verilog code describing a fully combinational binarized neural network.☆34Updated 7 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 4 months ago
- Fully Hardware-Based Stochastic Neural Network☆22Updated 5 months ago
- Fully opensource spiking neural network accelerator☆152Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆68Updated 2 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 6 years ago
- ☆58Updated 5 years ago
- FPGA Design of a Spiking Neural Network.☆41Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago
- ☆25Updated last year