HW Design Collateral for Caliptra RoT IP
☆154Sep 25, 2026Updated this week
Alternatives and similar repositories for caliptra-rtl
Users that are interested in caliptra-rtl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆53Updated this week
- Caliptra IP and firmware for integrated Root of Trust block☆478Updated this week
- Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test☆170Updated this week
- High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs☆28Updated this week
- Caliptra MCU Software☆41Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆63Updated this week
- ☆57Sep 15, 2026Updated last week
- Standardization of security reviews for datacenter products☆30Updated this week
- Linux applications to manage, test and develop devices supporting DMTF Security Protocol and Data Model (SPDM)☆21Jun 8, 2026Updated 3 months ago
- APB Logic☆29Updated this week
- ☆16May 25, 2026Updated 4 months ago
- ☆10Nov 2, 2023Updated 2 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆35Nov 3, 2025Updated 10 months ago
- VeeR EL2 Core☆346Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Filelist generator☆21Sep 14, 2026Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆101Aug 20, 2026Updated last month
- A simple superscalar out-of-order RISC-V microprocessor☆255Feb 24, 2025Updated last year
- OpenTitan: Open source silicon root of trust☆3,665Updated this week
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- High quality and composable RTL libraries in SystemVerilog☆55Updated this week
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- ☆25Sep 29, 2025Updated 11 months ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 11 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,068Updated this week
- Superscalar dual-issue RISC-V processor☆19Aug 4, 2026Updated last month
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆121Sep 24, 2025Updated last year
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Sep 12, 2026Updated 2 weeks ago
- A repository to define IETF RATS Concise Reference Integrity Manifest (CoRIM) Data Format Standard for supplying Reference Values and En…☆17Updated this week
- A Linux-capable RISC-V multicore for and by the world☆835Updated this week
- Security Project☆107Aug 28, 2026Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆684Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆426Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Dual-issue RV64IM processor for fun & learning☆65Jul 4, 2023Updated 3 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- SystemC/TLM-2.0 Co-simulation framework☆309Jun 26, 2026Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆174Updated this week
- ☆22Sep 26, 2025Updated last year
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆17Sep 27, 2022Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,706Updated this week