chipsalliance / Caliptra

Related projects ⓘ

Alternatives and complementary repositories for Caliptra

• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆97Updated last year
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆50Updated last month
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆40Updated last week
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆78Updated 3 weeks ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆76Updated this week
• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆82Updated 9 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆93Updated last month
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆195Updated this week
• riscv-software-src / riscof
  ☆64Updated 3 weeks ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆133Updated last year
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆29Updated 2 months ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆85Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆195Updated last week
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆112Updated last year
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆52Updated this week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆72Updated 2 months ago
• veryl-lang / veryl
  Veryl: A Modern Hardware Description Language
  ☆508Updated this week
• yupferris / kaze
  An HDL embedded in Rust.
  ☆194Updated 11 months ago
• cucapra / filament
  Fearless hardware design
  ☆160Updated last week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆116Updated 2 weeks ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆245Updated this week
• riscv / riscv-aia
  ☆80Updated last week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆218Updated 11 months ago
• SpinalHDL / NaxRiscv
  ☆269Updated last month
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆162Updated 2 weeks ago
• IBM / ACE-RISCV
  Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified…
  ☆30Updated 3 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆130Updated 2 weeks ago
• riscv / virtual-memory
  ☆35Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆150Updated 8 months ago
• embench / embench-iot
  The main Embench repository
  ☆258Updated 2 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆212Updated last week