Alternatives and similar repositories for pfr-wilson-city

Users that are interested in pfr-wilson-city are comparing it to the libraries listed below

• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆100Updated this week
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆39Updated 2 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆51Updated 6 months ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆48Updated 4 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆26Updated 5 years ago
• Pufferfish / tlm-of-a-pcie-rootcomplex-systemc
  A transaction level model of a PCI express root complex implemented in systemc
  ☆22Updated 11 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆21Updated 2 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆20Updated 4 years ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆104Updated 7 years ago
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆76Updated last month
• RSPwFPGAs / virtio-fpga-bridge
  Virtio front-end and back-end bridge, implemented with FPGA.
  ☆28Updated 4 years ago
• antmicro / rowhammer-tester
  ☆63Updated 2 months ago
• IntelLabs / c3-simulator
  C3-Simulator is a Simics-based functional simulator for the X86 C3 processor, including library and kernel support for pointer and data e…
  ☆19Updated 4 months ago
• quic / qbox
  Qbox
  ☆57Updated last week
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆58Updated 2 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆54Updated this week
• xyzxinyizhang / FPGA-SFP-communication-with-Aurora
  ☆19Updated 6 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆65Updated 2 years ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆35Updated last month
• Cosmos-OpenSSD / Cosmos-OpenSSD
  ☆43Updated 7 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 5 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated 11 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago