Alternatives and similar repositories for AX7Z035B_2023.1:

Users that are interested in AX7Z035B_2023.1 are comparing it to the libraries listed below

• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 7 months ago
• Aashish3970 / MNIST_FPGA
  3 layern artificial ANN to recognize handwritten digits and implement in FPGA
  ☆8Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆109Updated 10 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆32Updated 3 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆101Updated 5 years ago
• aquaxis / IPCORE
  ☆129Updated 9 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆199Updated 4 months ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆119Updated 3 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆48Updated 3 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆54Updated 8 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆146Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆96Updated 4 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆208Updated 7 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆142Updated 8 months ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆149Updated 4 months ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆136Updated 4 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆58Updated 3 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆167Updated last year
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆63Updated 5 years ago
• shun6-6 / Tri_Eth_UDP_pro_stack
  基于FPGA的三速以太网UDP协议栈设计
  ☆22Updated 11 months ago
• iharbour-heyaonan / FPGA_image_process
  FPGA实现简单的图像处理算法
  ☆41Updated last year
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆36Updated 2 years ago
• louisliuwei / PynqDocs
  PYNQ学习资料
  ☆162Updated 5 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆81Updated 5 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆192Updated last year
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆172Updated 11 months ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 2 years ago