Alternatives and similar repositories for course-lab_1

Users that are interested in course-lab_1 are comparing it to the libraries listed below

• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• bol-edu / 2022-fall-ntu
  ☆34Updated last year
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆123Updated last year
• cathalmccabe / PYNQ_tutorials
  ☆102Updated 2 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆159Updated 10 months ago
• bol-edu / HLS-SOC-Discussions
  Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.
  ☆56Updated 2 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆71Updated 5 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆168Updated 2 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆213Updated this week
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆144Updated 11 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆237Updated 5 months ago
• Xilinx / xup_embedded_system_design_flow
  AMD Xilinx University Program Embedded tutorial
  ☆42Updated 2 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆240Updated 2 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆72Updated 7 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆40Updated 3 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆43Updated 2 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆79Updated 7 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆80Updated 11 years ago
• jmduarte / HLS_hls4ml_Tutorial
  HLS & hls4ml Tutorial
  ☆15Updated 5 years ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆215Updated 6 years ago
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆20Updated 6 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆21Updated 4 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆92Updated 3 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆144Updated 6 years ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆241Updated 4 months ago
• yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynq
  Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
  ☆11Updated last year
• yutongshen / RISC-V_SoC
  ☆44Updated 2 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated 3 weeks ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago