guoyijiang / VerilogModule-IIC_MasterLinks
this repository is a project about iic master, created by gyj in second half of 2017
☆18Updated 7 years ago
Alternatives and similar repositories for VerilogModule-IIC_Master
Users that are interested in VerilogModule-IIC_Master are comparing it to the libraries listed below
Sorting:
- ☆23Updated 2 months ago
- ABP Accelerated VIP☆22Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆11Updated 4 years ago
- ☆20Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- ☆13Updated 6 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆15Updated 2 years ago
- ☆21Updated 5 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆21Updated last year
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- AHB Bus lite v3.0☆16Updated 6 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 6 years ago
- Generic AXI master stub☆19Updated 11 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆11Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆20Updated 8 years ago
- AXI Interconnect☆52Updated 4 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Updated 4 years ago
- ☆26Updated 4 years ago
- ☆21Updated 5 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- IP Catalog for Raptor.☆14Updated 9 months ago
- Verification IP for APB protocol☆69Updated 4 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆17Updated 5 years ago