guoyijiang / VerilogModule-IIC_Master

Related projects ⓘ

Alternatives and complementary repositories for VerilogModule-IIC_Master

• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆15Updated 10 years ago
• pulp-platform / apb_uart_sv
  ☆11Updated 5 years ago
• daviddhas / Some-useful-Perl-Scripts
  These scrpits will be extremly useful in parsing Verilog files
  ☆7Updated 9 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆29Updated 6 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆29Updated 4 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆44Updated 8 years ago
• wanderingnail / AXI_DMA
  ☆16Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆17Updated 5 years ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆21Updated 6 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆33Updated 2 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆9Updated last year
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆19Updated 5 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆20Updated 4 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• rgwan / AMBA
  Collection of IPs based on AMBA (AHB, APB, AXI) protocols
  ☆19Updated 7 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆33Updated 9 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆35Updated 7 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆17Updated 5 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆16Updated 6 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆16Updated last year
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆47Updated 5 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆46Updated 8 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆20Updated 4 years ago