Alternatives and similar repositories for VerilogModule-IIC_Master:

Users that are interested in VerilogModule-IIC_Master are comparing it to the libraries listed below

• pulp-platform / apb_uart_sv
  ☆11Updated 5 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆9Updated 3 years ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆15Updated 11 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• rgwan / AMBA
  Collection of IPs based on AMBA (AHB, APB, AXI) protocols
  ☆19Updated 7 years ago
• lauchinyuan / Asymmetric_async_FIFO
  asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…
  ☆15Updated last year
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆9Updated last year
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆35Updated 7 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆32Updated 2 weeks ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 6 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆28Updated 3 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆36Updated 2 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆19Updated 10 months ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆44Updated 8 years ago
• daviddhas / Some-useful-Perl-Scripts
  These scrpits will be extremly useful in parsing Verilog files
  ☆7Updated 9 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆42Updated 10 months ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆26Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆56Updated 4 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• wanderingnail / AXI_DMA
  ☆16Updated 2 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆12Updated 5 years ago
• aignacio / ahb_lite_bus
  AHB Bus lite v3.0
  ☆14Updated 5 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆20Updated 5 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆19Updated 5 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• pulp-platform / axi2apb
  ☆18Updated 4 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆25Updated 3 years ago