guoyijiang / VerilogModule-IIC_Master
this repository is a project about iic master, created by gyj in second half of 2017
☆15Updated 6 years ago
Alternatives and similar repositories for VerilogModule-IIC_Master:
Users that are interested in VerilogModule-IIC_Master are comparing it to the libraries listed below
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆9Updated 3 years ago
- ☆11Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆19Updated 2 years ago
- Implementation of the PCIe physical layer☆37Updated 2 months ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- System Verilog and Emulation. Written all the five channels.☆33Updated 8 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆17Updated 4 years ago
- ☆21Updated 5 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- A 32 point radix-2 FFT module written in Verilog☆22Updated 4 years ago
- ☆25Updated 3 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- AXI Interconnect☆47Updated 3 years ago
- DMA Hardware Description with Verilog☆13Updated 5 years ago
- AHB Bus lite v3.0☆15Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆66Updated last year
- 异步FIFO的内部实现☆24Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆17Updated 9 months ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago