guoyijiang / VerilogModule-IIC_MasterLinks
this repository is a project about iic master, created by gyj in second half of 2017
☆17Updated 7 years ago
Alternatives and similar repositories for VerilogModule-IIC_Master
Users that are interested in VerilogModule-IIC_Master are comparing it to the libraries listed below
Sorting:
- ABP Accelerated VIP☆22Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆10Updated 3 years ago
- These scrpits will be extremly useful in parsing Verilog files☆7Updated 10 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- AHB Bus lite v3.0☆16Updated 5 years ago
- ☆20Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- ☆13Updated 6 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- AXI4 with a FIFO integrated with VIP☆19Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- ☆21Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- Verification IP for UART protocol☆18Updated 4 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆11Updated 7 years ago
- Implementation of the PCIe physical layer☆45Updated this week
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆14Updated this week
- 10 Gigabit Ethernet MAC Core UVM Verification☆13Updated last year
- ☆25Updated 4 years ago