Ummidichandrika / RTL-ExamplesLinks
☆11Updated last year
Alternatives and similar repositories for RTL-Examples
Users that are interested in RTL-Examples are comparing it to the libraries listed below
Sorting:
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Trying to get a new skill☆31Updated last year
- Design of LDO using open source SKY130PDK☆13Updated last year
- This is a passion project where I aim to explore the RTL design topics of my interest.☆14Updated 8 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Updated 2 years ago
- ☆17Updated 8 months ago
- Custom IC Design Platform☆46Updated 2 weeks ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆108Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated last year
- Python Tool for UVM Testbench Generation☆55Updated last year
- ☆47Updated last year
- ☆116Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆17Updated 2 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆52Updated 2 months ago
- ☆175Updated 3 years ago
- ☆44Updated 2 years ago
- ☆41Updated 3 years ago
- Architectural design of data router in verilog☆32Updated 6 years ago
- Structured UVM Course☆58Updated 2 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆35Updated 7 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 3 years ago
- Verilog RTL Design☆46Updated 4 years ago
- Interface definitions for VHDL-2019.☆34Updated 3 weeks ago
- ☆86Updated last year
- System Verilog using Functional Verification☆12Updated last year