Alternatives and similar repositories for VLSI

Users that are interested in VLSI are comparing it to the libraries listed below

• barbedo / verilog-book
  Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
  ☆23Updated 7 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 4 years ago
• ashishrana160796 / verilog-starter-tutorials
  Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
  ☆59Updated 4 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆57Updated 2 years ago
• maazm007 / 100Daysof_RTL
  The Repository contains the code of various Digital Circuits
  ☆11Updated 2 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆49Updated last year
• avashist003 / SystemVerilog_Design_Verification
  Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog
  ☆25Updated 3 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆72Updated 6 years ago
• HunterBitos / Implementation-of-AMBA-AXI3-protocol
  Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…
  ☆13Updated 7 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆20Updated 2 years ago
• eescottie / opensrc_analog
  Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design
  ☆11Updated 2 months ago
• AhmedAmrAbdellatif / Multi-Clock-Domain-System
  Design & Implementation of Multi Clock Domain System using Verilog HDL
  ☆13Updated last year
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆26Updated 3 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆44Updated 3 years ago
• Suntrakanesh / System-Verilog-bootcamp
  System Verilog BootCamp
  ☆25Updated 3 years ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆15Updated 3 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• kunalg123 / sky130RTLDesignAndSynthesisWorkshop
  ☆17Updated 3 years ago
• mihir8181 / VerilogHDL-Codes
  Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
  ☆39Updated 6 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆59Updated 2 years ago
• digital-design-hq / Digital-Resources
  ☆61Updated 3 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆79Updated last year
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆109Updated last year
• taneroksuz / cpu-medium
  6-stage in-order dual-issue superscalar risc-v cpu with floating point unit
  ☆14Updated last week
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago
• andrsmllr / magic_vlsi_examples
  Some simple examples for the Magic VLSI physical chip layout tool.
  ☆30Updated 4 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• stevehoover / makerchip_examples
  ☆19Updated 2 weeks ago
• mabrains / caravel_user_project_ldo
  Completed LDO Design for Skywaters 130nm
  ☆16Updated 2 years ago