SubZer0811 / VLSILinks
All the projects and assignments done as part of VLSI course.
☆20Updated 5 years ago
Alternatives and similar repositories for VLSI
Users that are interested in VLSI are comparing it to the libraries listed below
Sorting:
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 4 years ago
- RISC V core implementation using Verilog.☆28Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- System Verilog BootCamp☆25Updated 4 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆59Updated 3 years ago
- Structured UVM Course☆58Updated 2 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Updated 3 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Updated 4 years ago
- ☆41Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- Implementation of a cache memory in verilog☆15Updated 8 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆36Updated 6 years ago
- ☆17Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- To design test bench of the APB protocol☆18Updated 5 years ago
- The Repository contains the code of various Digital Circuits☆11Updated 2 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆61Updated 5 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated last year
- Design Verification Engineer interview preparation guide.☆43Updated 6 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆124Updated 3 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Updated 7 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 3 years ago