LLM-Aided FPGA Design for Signal Processing Applications
☆35Jun 4, 2025Updated last year
Alternatives and similar repositories for pulseDetector
Users that are interested in pulseDetector are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LLM-Aided FPGA Design and Debug Flow☆43Aug 1, 2025Updated last year
- LLM-Aided FPGA Design Optimization☆17Jun 4, 2025Updated last year
- A Comprehensive Comparative Study of LLM-Aided FPGA Design Flow☆13Jul 14, 2025Updated last year
- ☆15Aug 1, 2024Updated 2 years ago
- ☆10Jun 26, 2025Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Multi-bit Synchronization across Clock Domains☆10May 18, 2018Updated 8 years ago
- This repo will show how to build FFTW on Zynq☆20Jan 31, 2025Updated last year
- End-to-End Open-Source I2C GPIO Expander☆45Sep 24, 2026Updated last month
- This repository provides a Linux kernel driver for AXI UART Lite accessed via PCIe XDMA. It enables efficient DMA-based UART communicatio…☆16May 2, 2025Updated last year
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆96Feb 9, 2026Updated 8 months ago
- Resources for my first book☆22Jun 21, 2023Updated 3 years ago
- 郑州大学疫情自动打卡☆10Sep 16, 2023Updated 3 years ago
- 从零快速使用Ubuntu，搭建深度学习环境，持续更新中☆13Apr 18, 2023Updated 3 years ago
- An implementation of the CCSDS 123.0-B-1 standard for FPGA with parallel capabilities.☆12Jun 1, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago
- ☆22Aug 4, 2022Updated 4 years ago
- Library for exact linear algebra, a C++ template-library based originally on LinBox intended for F4-like implementations☆18Dec 15, 2012Updated 13 years ago
- 2014 UCSC Extension FPGA class☆28Oct 23, 2015Updated 11 years ago
- [FCCM 2025 Best Paper Nominee] AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGA…☆14Jul 16, 2025Updated last year
- End-to-end LoRa PHY modem simulator in base MATLAB — full TX/RX chain, CFO/STO/SFO synchronization, digital AGC, crystal-oscillator impai…☆18Jul 7, 2026Updated 3 months ago
- 5G NR SSB Scanner and Capturer☆35Sep 2, 2025Updated last year
- FPGA Developer board repository☆25Oct 15, 2026Updated 2 weeks ago
- High Reliability IP Modem☆32Sep 2, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An ANSI C implementation of Hamming codes☆15Oct 18, 2019Updated 7 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆18Mar 17, 2019Updated 7 years ago
- An install script to install Gnu Radio and BladeRF on a Raspberry Pi☆15Nov 4, 2023Updated 2 years ago
- QCX FT8 transmission suite☆15Mar 26, 2020Updated 6 years ago
- ☆18Nov 20, 2022Updated 3 years ago
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆15Jul 17, 2023Updated 3 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- One-menu RTX 5090 installer for the abliterated Qwen3.8-Flash-Next on fngine: pinned build with isolated CUDA, verified download, serving…☆13Oct 15, 2026Updated 2 weeks ago
- ☆16May 23, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The OpenCpuX API☆10Jun 26, 2026Updated 4 months ago
- Verilog interface for HC-SR04 Ultrasonic Ranging Module☆10Aug 3, 2023Updated 3 years ago
- ☆15Oct 12, 2026Updated 2 weeks ago
- ☆20Sep 18, 2024Updated 2 years ago
- Top level for the November shuttle☆13Nov 20, 2021Updated 4 years ago
- Second version of Frequency Modulated Continuous Wave Radar Hardware Design's Python analysis☆29Aug 4, 2026Updated 2 months ago
- NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enable…☆18Aug 16, 2026Updated 2 months ago