LLM-Aided FPGA Design for Signal Processing Applications
☆35Jun 4, 2025Updated last year
Alternatives and similar repositories for pulseDetector
Users that are interested in pulseDetector are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LLM-Aided FPGA Design and Debug Flow☆43Aug 1, 2025Updated last year
- ☆15Aug 1, 2024Updated 2 years ago
- This repo will show how to build FFTW on Zynq☆19Jan 31, 2025Updated last year
- End-to-End Open-Source I2C GPIO Expander☆45Sep 24, 2026Updated 2 weeks ago
- [FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs☆14Jun 26, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆21Aug 4, 2022Updated 4 years ago
- Bilingual FPGA-based SDR course for Zynq with labs, hardware workflow, MATLAB/Simulink and DSP implementation track☆98Updated this week
- An install script to install Gnu Radio and BladeRF on a Raspberry Pi☆15Nov 4, 2023Updated 2 years ago
- End-to-end LoRa PHY modem simulator in base MATLAB — full TX/RX chain, CFO/STO/SFO synchronization, digital AGC, crystal-oscillator impai…☆17Jul 7, 2026Updated 3 months ago
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 3 years ago
- High Reliability IP Modem☆31Sep 2, 2025Updated last year
- ☆16May 23, 2024Updated 2 years ago
- An ANSI C implementation of Hamming codes☆15Oct 18, 2019Updated 6 years ago
- ☆18Nov 20, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆19Mar 17, 2019Updated 7 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- Notes on the Eclypse Z7 development board☆17Apr 9, 2026Updated 6 months ago
- ☆17Feb 3, 2022Updated 4 years ago
- Top level for the November shuttle☆13Nov 20, 2021Updated 4 years ago
- NeTV2 SoC based on LiteX☆17Jul 17, 2018Updated 8 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Sep 1, 2026Updated last month
- Python script for QPSK modulation and demodulation☆12May 27, 2020Updated 6 years ago
- Space invaders hardware clone on the DE2-115 FPGA dev board with a USB keyboard and VGA output.☆13Feb 16, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Localization of a GNSS denied UAV relative to a Moving Local Reference Frame in an Offshore Environment☆14Sep 1, 2025Updated last year
- Open-source inmarsat-C cli decoder, based on inmarsatc library.☆18Jul 30, 2022Updated 4 years ago
- SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs☆19May 23, 2024Updated 2 years ago
- A wrapper around Minecraft Raspberry Pi to get it working on Novena☆11Sep 25, 2013Updated 13 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 7 months ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆10Sep 17, 2019Updated 7 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 7 years ago
- ☆15Aug 14, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Interactive 3D Layout Viewer for GDSII☆20Jun 14, 2024Updated 2 years ago
- Open source graphical interface to various DFT/Quantum chemistry codes☆18Dec 8, 2022Updated 3 years ago
- Active Learning Interface for Circuits and Electronics☆19Feb 18, 2023Updated 3 years ago
- ☆12Jan 24, 2021Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Updated FPGA source code and binaries for UHD B220 Clone with XC7A200T+AD9361☆61Jun 8, 2025Updated last year
- Maltlab based software GNSS receiver for Nooelec SDR front ends☆14Mar 4, 2025Updated last year