Alternatives and similar repositories for pulseDetector:

Users that are interested in pulseDetector are comparing it to the libraries listed below

• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆37Updated 3 weeks ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆80Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆39Updated last year
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆94Updated last week
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆29Updated 4 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆76Updated last month
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆28Updated 11 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆70Updated 9 months ago
• efard / DSPHDL
  ☆41Updated last year
• ECASLab / cynq
  PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.
  ☆23Updated last month
• hibagus / 64pointFFTProcessor
  Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
  ☆29Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆17Updated 2 years ago
• Xilinx / ZCU111-PYNQ
  Board files to build the ZCU111 PYNQ image
  ☆18Updated 2 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 2 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆57Updated 11 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆25Updated 4 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆104Updated 7 months ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆121Updated 2 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆24Updated 3 weeks ago
• ATaylorCEngFIET / Vitis_Hero
  ☆25Updated 2 years ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆58Updated 4 months ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆48Updated last year
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆44Updated this week
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 2 weeks ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆46Updated this week
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆47Updated 8 years ago
• lowRISC / ariane-ethernet
  open-source Ethenet media access controller for Ariane on Genesys-2
  ☆19Updated 5 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆101Updated last year