scottinet / espresso-logic-minimizerLinks
A Node.js bridge to the Espresso heuristic logic minimizer original C code
☆41Updated 3 years ago
Alternatives and similar repositories for espresso-logic-minimizer
Users that are interested in espresso-logic-minimizer are comparing it to the libraries listed below
Sorting:
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆167Updated 5 years ago
- An advanced header-only exact synthesis library☆30Updated 3 years ago
- A circuit toolkit☆106Updated 5 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆38Updated last year
- C++ truth table library☆64Updated 5 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated this week
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- ☆104Updated 3 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆39Updated 10 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- 🔁 elastic circuit toolchain☆32Updated last year
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆89Updated this week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Debuggable hardware generator☆70Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- This is the Verilog 2005 parser used by VerilogCreator☆15Updated 6 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆32Updated 4 years ago
- A time-predictable processor for mixed-criticality systems☆60Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆101Updated this week
- Demo SoC for SiliconCompiler.☆62Updated last week
- OpenFPGA☆34Updated 7 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 9 months ago
- D3.js and ELK based schematic visualizer☆111Updated last year
- ACT hardware description language and core tools.☆121Updated 2 weeks ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 weeks ago
- ☆59Updated 3 years ago