[DATE'25, ICCAD'25] An embedded FPGA-based LLM accelerator capable of supporting Llama2-7B
☆150May 1, 2026Updated last month
Alternatives and similar repositories for llama-fpga
Users that are interested in llama-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆37Nov 13, 2025Updated 7 months ago
- The MEISHA V100 contains four 64-bit RISC-V RV64GC,a 5-stage in-order scalar pipeline, comprehensive peripherals and interfaces. The syst…☆20Feb 2, 2026Updated 4 months ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Official code of paper "MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator", ASP-DAC 2025☆37Oct 15, 2025Updated 7 months ago
- Quantum Binary Neural Networks☆16Oct 20, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- FINN+ is an extended version of FINN, a dataflow compiler for QNN inference on FPGAs. It is maintained by a group of researchers at Pader…☆54Updated this week
- ☆11Jun 3, 2025Updated last year
- Code implementing a neuromorphic, spiking backpropagation algorithm on Intel's neuromorphic research processor, codenamed Loihi☆16Nov 14, 2024Updated last year
- ☆11Jan 25, 2023Updated 3 years ago
- 第八届集创赛紫光同创杯音频处理国家二等奖☆26Oct 15, 2024Updated last year
- A nest brain simulator based on FPGA(LIF NEURON)☆16Dec 14, 2021Updated 4 years ago
- An Open-Source Processor for Accelerating Spiking Neural Network☆13Sep 30, 2022Updated 3 years ago
- SNN on FPGA☆13Apr 26, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 基于FPGA的FFT算法并行优化☆13Mar 7, 2024Updated 2 years ago
- ☆30Jun 19, 2025Updated 11 months ago
- Simple implementation of the VGG16 net from scratch written in C++☆14Oct 17, 2020Updated 5 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆114Apr 28, 2025Updated last year
- ☆37Nov 11, 2018Updated 7 years ago
- BitNet a4.8 Implementation in one file of pytorch☆21Jan 13, 2025Updated last year
- Serpens is an HBM FPGA accelerator for SpMV☆23Jul 26, 2024Updated last year
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 8 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated 2 years ago
- My code repositry for common use.☆23Dec 31, 2021Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆24Apr 25, 2025Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- ☆10Apr 4, 2025Updated last year
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Feb 22, 2026Updated 3 months ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆14Aug 23, 2024Updated last year
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆14Jul 16, 2024Updated last year
- 第八届集创赛紫光同创杯国二FPGA部分☆35Sep 23, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Apr 6, 2020Updated 6 years ago
- ☆38Sep 17, 2024Updated last year
- 我的一生一芯项目☆16Dec 14, 2021Updated 4 years ago
- TFHE is a popular algorithm for homomorphic encryption. Staring with a C/C++ specification of TFHE to be provided, This project rewrite t…☆21May 27, 2024Updated 2 years ago
- Code and data for the paper: DTSM: Toward Dense Table Structure Recognition with Text Query Encoder and Adjacent Feature Aggregator☆13Apr 28, 2024Updated 2 years ago
- ☆29Nov 14, 2025Updated 7 months ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆20Jan 17, 2025Updated last year