Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
☆10Jan 14, 2024Updated 2 years ago
Alternatives and similar repositories for eccExamples
Users that are interested in eccExamples are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Sep 24, 2018Updated 7 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆24Dec 17, 2019Updated 6 years ago
- Intel(R) 8051 Instruction Set Simulator☆14Aug 17, 2023Updated 2 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 11 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Aug 23, 2019Updated 6 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 7 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆29Feb 2, 2026Updated 2 months ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated last year
- my emacs config☆13Mar 12, 2026Updated last month
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 8 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆14Dec 16, 2020Updated 5 years ago
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆10May 24, 2021Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆15Jun 28, 2021Updated 4 years ago
- Dilithium is a digital signature scheme that is strongly secure under chosen message attacks based on the hardness of lattice problems ov…☆15Jul 28, 2023Updated 2 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- ☆13Apr 24, 2022Updated 4 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- A simple PDM microphone interface on FPGA☆14Jan 16, 2022Updated 4 years ago
- Some useful functions to process pdf file☆20Sep 13, 2025Updated 7 months ago
- Implementing the MATLAB example using 5G toolbox and Deep Learning Tolbox☆15Sep 1, 2021Updated 4 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆23Feb 20, 2017Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Reed Solomon Decoder (204,188)☆13Jul 17, 2014Updated 11 years ago
- asynchronous fifo based on verilog☆15Apr 14, 2022Updated 4 years ago
- General Purpose I/O agent written in UVM☆17Jun 29, 2017Updated 8 years ago
- Forces DeepSeek R1 models to engage in extended reasoning by intercepting early termination tokens.☆19Feb 12, 2025Updated last year
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- Polar Codes Implementation on Vhdl☆14Jun 4, 2016Updated 9 years ago
- this repository is vim cfg for verilog.☆55Apr 24, 2026Updated last week
- This project is made to generate Polar decoders (unrolled decoders).☆15May 31, 2025Updated 11 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆146Mar 6, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verification IP project for I3C protocol☆27Feb 13, 2026Updated 2 months ago
- ☆18Aug 26, 2016Updated 9 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- 16 bit CPU created in Vivado with Verilog☆22Jun 30, 2022Updated 3 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 7 years ago
- ☆24Nov 4, 2023Updated 2 years ago
- few python scripts to clone all IP cores from opencores.org☆27Jan 8, 2024Updated 2 years ago