Lcrypto / FEC-Archive-Verilog
Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code (24), 4-dimension 8-ary phase shift keying trellis coded modulation (TCM_4D_8PSK), BCH, CCSDS and recursive systematic convolutional (RSC) Turbo co…
☆53Updated last year
Related projects ⓘ
Alternatives and complementary repositories for FEC-Archive-Verilog
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆85Updated 4 months ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆43Updated 7 months ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆44Updated 7 years ago
- IEEE 802.11 OFDM-based transceiver system☆30Updated 6 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆20Updated last month
- Polar Codes Implementation on Vhdl☆12Updated 8 years ago
- Verilog实现OFDM基带☆39Updated 8 years ago
- NMS_decode☆11Updated 4 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆52Updated 5 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆22Updated 5 years ago
- Wi-Fi LDPC codec Verilog IP core☆15Updated 5 years ago
- 最小和算法实现☆11Updated 4 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆12Updated 4 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆41Updated 6 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆36Updated 5 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆21Updated 3 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- The source codes of the fast x86 LDPC decoder published☆25Updated 4 years ago
- Hardware Viterbi Decoder in verilog☆22Updated 5 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆90Updated last year
- Low Density Parity Check Decoder☆16Updated 8 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆15Updated 3 years ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆62Updated 4 months ago
- FIR implemention with Verilog☆44Updated 5 years ago
- IEEE 802.16 OFDM-based transceiver system☆20Updated 5 years ago
- Playground for implementing LDPC codes on FPGA☆15Updated last year
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆40Updated 2 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆11Updated 4 years ago