Lcrypto / FEC-Archive-VerilogLinks
Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code (24), 4-dimension 8-ary phase shift keying trellis coded modulation (TCM_4D_8PSK), BCH, CCSDS and recursive systematic convolutional (RSC) Turbo co…
☆69Updated 2 years ago
Alternatives and similar repositories for FEC-Archive-Verilog
Users that are interested in FEC-Archive-Verilog are comparing it to the libraries listed below
Sorting:
- NMS_decode☆13Updated 4 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆105Updated last year
- Polar Codes Implementation on Vhdl☆13Updated 9 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆50Updated 7 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- IEEE 802.11 OFDM-based transceiver system☆34Updated 7 years ago
- 最小和算法实现☆10Updated 4 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆58Updated 6 years ago
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- Verilog实现OFDM基带☆44Updated 9 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 5 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆46Updated 6 years ago
- ☆12Updated 3 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆22Updated 4 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆38Updated 6 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆50Updated 2 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆37Updated 8 months ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Updated 4 years ago
- Hardware Viterbi Decoder in verilog☆26Updated 6 years ago
- Low Density Parity Check Decoder☆16Updated 8 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆103Updated 2 years ago
- Verilog based BCH encoder/decoder☆120Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 4 years ago
- An RFSoC Frequency Planner developed using Python.☆28Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …☆16Updated 2 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago