tgrogers / ece695-2021View external linksLinks
Programming and Assignment Material for ECE 695
☆17Apr 23, 2021Updated 4 years ago
Alternatives and similar repositories for ece695-2021
Users that are interested in ece695-2021 are comparing it to the libraries listed below
Sorting:
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- A Heterogeneous GPU Platform for Chipyard SoC☆42Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Mar 29, 2025Updated 10 months ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Notes on several classes at Purdue☆15Dec 10, 2025Updated 2 months ago
- GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated…☆67Jan 22, 2026Updated 3 weeks ago
- ☆27Jan 22, 2023Updated 3 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆49Jan 20, 2026Updated 3 weeks ago
- 经典的嵌入式OS - ucos-II 2.52版本全注释，仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- Teaching cars soccer☆12Apr 20, 2024Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- livecoding talk for oscon 2018☆10Jul 18, 2018Updated 7 years ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Jan 17, 2024Updated 2 years ago
- ☆13May 8, 2025Updated 9 months ago
- Deep Learning Framework with a specialisation aimed for Binarized Neural Networks.☆11Jan 9, 2022Updated 4 years ago
- ☆12Apr 6, 2025Updated 10 months ago
- Perceptron-based branch predictor written in C++☆12Dec 14, 2016Updated 9 years ago
- ☆10Jun 4, 2021Updated 4 years ago
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 4 years ago
- simple 4-BIT CPU with 74-serials chip，origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- Simple PyTorch profiler that combines DeepSpeed Flops Profiler and TorchInfo☆11Feb 12, 2023Updated 3 years ago
- Deep learning algorithms developed by ourselves from scratch by C++. No deep learning frameworks are used.☆10Aug 3, 2020Updated 5 years ago
- Code for "Message Scheduling for Performant, Many-Core Belief Propagation"☆12Oct 25, 2019Updated 6 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Apr 9, 2019Updated 6 years ago