tgrogers / ece695-2021Links
Programming and Assignment Material for ECE 695
☆17Updated 4 years ago
Alternatives and similar repositories for ece695-2021
Users that are interested in ece695-2021 are comparing it to the libraries listed below
Sorting:
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 3 weeks ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆102Updated 6 months ago
- ☆107Updated last year
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 8 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆20Updated 7 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆48Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Updated last year
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆100Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆167Updated 9 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆76Updated 6 months ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆37Updated 11 months ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- ☆49Updated 3 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated last month
- ☆155Updated 9 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- A co-design architecture on sparse attention☆54Updated 4 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 5 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆79Updated 6 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆59Updated last month
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆47Updated 2 months ago
- This GitHub repo contains the artifact for CPElide, which appears at MICRO '24☆12Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆41Updated 2 years ago
- ☆47Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year