Rishabh-zhcet / 3DOF_RoboticArmFPGALinks
This repository contains the details of controlling a 3-DOF robotic arm with 4 servo motors using FPGA. The design is execute using the Nexys-4 DDR Artix-7 FPGA of Xilinx. This repo contails all the files necessary to complete the project such as Verilog code, test bench and constrain file.
☆19Updated 3 years ago
Alternatives and similar repositories for 3DOF_RoboticArmFPGA
Users that are interested in 3DOF_RoboticArmFPGA are comparing it to the libraries listed below
Sorting:
- Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…☆23Updated last year
- opensource EDA tool flor VLSI design☆34Updated 2 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆215Updated 4 months ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆29Updated 2 months ago
- 100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…☆27Updated 2 years ago
- ☆13Updated 10 months ago
- FPGA Design of a Neural Network for Color Detection☆78Updated 8 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆96Updated 2 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆27Updated 2 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆67Updated 3 years ago
- ☆116Updated last year
- ☆41Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆31Updated 10 months ago
- SystemVerilog Tutorial☆176Updated last week
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆119Updated 3 years ago
- FIR band-pass filter using Verilog HDL.☆12Updated 5 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆26Updated last year
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆48Updated 6 months ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated 2 years ago
- ☆16Updated last year
- Vitis Model Composer Examples and Tutorials☆107Updated last week
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆141Updated last week
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year
- This repo provide an index of VLSI content creators and their materials☆157Updated last year
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆19Updated 2 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆272Updated 4 months ago
- ☆18Updated 5 months ago
- learn the combinational and sequential logic circuit.☆17Updated 2 months ago
- UVM and System Verilog Manuals☆44Updated 6 years ago
- ☆289Updated last year