Rishabh-zhcet / 3DOF_RoboticArmFPGA
This repository contains the details of controlling a 3-DOF robotic arm with 4 servo motors using FPGA. The design is execute using the Nexys-4 DDR Artix-7 FPGA of Xilinx. This repo contails all the files necessary to complete the project such as Verilog code, test bench and constrain file.
☆16Updated 2 years ago
Alternatives and similar repositories for 3DOF_RoboticArmFPGA:
Users that are interested in 3DOF_RoboticArmFPGA are comparing it to the libraries listed below
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆14Updated 2 months ago
- ☆27Updated 9 months ago
- ☆12Updated last month
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆23Updated 6 years ago
- Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…☆22Updated 8 months ago
- Trying to get a new skill☆19Updated 3 weeks ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆30Updated 4 years ago
- UART implementation using verilog☆9Updated last year
- opensource EDA tool flor VLSI design☆31Updated last year
- 100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…☆26Updated last year
- Lecture about FIR filter on an FPGA☆11Updated 8 months ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆13Updated last year
- Verilog HDL files☆114Updated 7 months ago
- ☆13Updated 2 years ago
- ☆16Updated last year
- FPGA Design of a Neural Network for Color Detection☆73Updated 8 months ago
- Verilog library for developing robotics applications using FPGAs☆65Updated 6 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆32Updated last year
- Architectural design of data router in verilog☆28Updated 5 years ago
- RISC-V-5 stage pipelined in verilog☆11Updated 4 years ago
- ☆105Updated last year
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆53Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆62Updated last year
- SystemVerilog Tutorial☆120Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆116Updated 5 months ago
- ☆16Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆23Updated 8 months ago
- This repo provide an index of VLSI content creators and their materials☆140Updated 5 months ago
- ☆10Updated 8 months ago