Alternatives and similar repositories for 3DOF_RoboticArmFPGA:

Users that are interested in 3DOF_RoboticArmFPGA are comparing it to the libraries listed below

• maazm007 / vsdsquadron-mini-internship
  VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
  ☆27Updated 11 months ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆31Updated 4 years ago
• amsacks / OV7670-camera
  A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …
  ☆15Updated 2 years ago
• Manish4403 / RISC_V_with_ICACHE
  ☆13Updated 5 months ago
• Marco-Winzker / NN_Pattern_FPGA
  Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…
  ☆23Updated 11 months ago
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆28Updated last year
• TheLeopardsH / RISC-V-5-stage-pipelined-in-verilog
  RISC-V-5 stage pipelined in verilog
  ☆11Updated 4 years ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated 11 months ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆19Updated last year
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆32Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆110Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆142Updated this week
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• MMujtabaRoohani / RISC-V-Processor
  A verilog based 5-stage pipelined RISC-V Processor code.
  ☆23Updated 5 years ago
• Marco-Winzker / NN_RGB_FPGA
  FPGA Design of a Neural Network for Color Detection
  ☆75Updated 3 months ago
• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 2 weeks ago
• yigitbektasgursoy / Motion_Estimation_Hardware_Verilog
  Motion Estimation implementation by using Verilog HDL
  ☆10Updated 10 months ago
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆198Updated last year
• sarthak268 / Embedded_Logic_and_Design
  This repository contains all labs done as a part of the Embedded Logic and Design course.
  ☆23Updated 6 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆61Updated 3 years ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• mehwish411 / 5-Staged-Pipelined-RISC-V-32I-Processor
  5 stage pipeline implementation of RISC-V 32I Processor.
  ☆10Updated 5 months ago
• arunkpv / vsd-hdp
  ☆16Updated 9 months ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆42Updated last year
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆17Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆86Updated last year
• pendkeomkar / SPI
  Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…
  ☆18Updated 6 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 3 years ago
• Xilinx / kria-vitis-platforms
  Kria Vitis platforms and overlays
  ☆99Updated last month