andrewandrepowell / zybo_petalinux_video_hls
Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.
☆25Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for zybo_petalinux_video_hls
- MIPI CSI-2 RX☆29Updated 3 years ago
- HOG + SVM on FPGA☆25Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.☆20Updated 8 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆98Updated 4 years ago
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago
- ☆52Updated 2 years ago
- OV7670 Camera Module Initialize with XILINX ZYNQ Driver☆11Updated 8 years ago
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 5 years ago
- ☆53Updated 2 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆51Updated 3 years ago
- ☆22Updated 8 years ago
- A real time Histogram of Oriented Gradients Implementation on FPGA☆30Updated 6 years ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆67Updated 2 years ago
- Verilog modules required to get the OV7670 camera working☆63Updated 6 years ago
- Video Stream Scaler☆40Updated 10 years ago
- ☆82Updated 4 years ago
- A multi-board Extended Kalman Filter (EKF)☆28Updated 6 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆37Updated 7 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆39Updated 7 years ago
- Verilog Code for a JPEG Decoder☆31Updated 6 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated this week
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago