Alternatives and similar repositories for elf-bootloader

Users that are interested in elf-bootloader are comparing it to the libraries listed below

• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆90Updated 4 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆41Updated 4 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆60Updated 6 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆44Updated 5 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 10 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆78Updated last year
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 6 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆38Updated 3 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• VideoGPU / FMC_MIPI
  FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface
  ☆17Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• ChinaQMTECH / ZYJZGW_Kintex-7_XC7K325T_Starter_Kit
  ☆16Updated 3 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆63Updated 2 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆38Updated 4 years ago
• mnentwig / busbridge3
  Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency
  ☆18Updated 6 years ago
• codeshaa / 16-bit-HDLC-using-VHDL
  High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
  ☆28Updated 8 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆32Updated 3 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• Wren6991 / HyperRam
  simple hyperram controller
  ☆11Updated 6 years ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆20Updated 4 months ago
• lvgl / lv_port_xilinx_zedboard_vitis
  This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
  ☆25Updated last year
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆27Updated 5 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 2 months ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 11 years ago