MuhammadMajiid / UARTLinks
UART implementation using verilog
☆22Updated 2 years ago
Alternatives and similar repositories for UART
Users that are interested in UART are comparing it to the libraries listed below
Sorting:
- Structured UVM Course☆44Updated last year
- ☆12Updated 3 months ago
- This is a detailed SystemVerilog course☆113Updated 4 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- APB master and slave developed in RTL.☆17Updated 3 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆132Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆102Updated 2 years ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆43Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆65Updated 4 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆83Updated 2 years ago
- ☆17Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- SystemVerilog Tutorial☆159Updated 2 months ago
- ☆33Updated last month
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆62Updated 2 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆15Updated 2 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆32Updated last week