MuhammadMajiid / UART
UART implementation using verilog
☆16Updated 2 years ago
Alternatives and similar repositories for UART:
Users that are interested in UART are comparing it to the libraries listed below
- ☆12Updated this week
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆68Updated last year
- opensource EDA tool flor VLSI design☆32Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆17Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 2 weeks ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 4 months ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- UVM and System Verilog Manuals☆40Updated 6 years ago
- Complete tutorial code.☆17Updated 11 months ago
- ☆40Updated last year
- Verilog Fundamentals Explained for Beginners and Professionals☆21Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆10Updated 7 months ago
- Structured UVM Course☆39Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- ☆16Updated 8 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆17Updated 11 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 2 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆36Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆17Updated 9 months ago
- Implementation of RISC-V RV32I☆16Updated 2 years ago
- ☆14Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- A complete UVM TB for verification of single port 64KB RAM☆15Updated 3 years ago
- ☆10Updated 2 years ago