UART implementation using verilog
☆38Feb 14, 2023Updated 3 years ago
Alternatives and similar repositories for UART
Users that are interested in UART are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- A simple implementation of a UART modem in Verilog.☆185Nov 10, 2021Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆20Sep 2, 2023Updated 2 years ago
- ☆15May 8, 2018Updated 8 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆36Oct 29, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Simple 8-bit UART realization on Verilog HDL.☆118Apr 27, 2024Updated 2 years ago
- Explore microcontroller architecture and ARM Cortex interfacing in this comprehensive workshop. Sessions cover topics like C basics, ARM …☆11Dec 25, 2024Updated last year
- Implementation of 5 Stage 32I RISC V Pipeline Processor.☆30Sep 6, 2024Updated last year
- Structured UVM Course☆72Jan 4, 2024Updated 2 years ago
- ESP32 esp-idf MPU6050 component☆11Mar 28, 2022Updated 4 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- UART design in SV and verification using UVM and SV☆58Nov 30, 2019Updated 6 years ago
- ☆53Aug 7, 2025Updated 10 months ago
- APB master and slave developed in RTL.☆25Oct 25, 2025Updated 7 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆82Dec 14, 2023Updated 2 years ago
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆16Mar 15, 2021Updated 5 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆30Dec 5, 2024Updated last year
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- Submission repo for Coderspree☆21Jul 10, 2022Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆13Dec 31, 2023Updated 2 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆19Jun 24, 2021Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Verilog UART☆198Jun 4, 2013Updated 13 years ago
- RV64IMAC modelling using System Verilog HDL☆26Aug 10, 2024Updated last year
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆15May 22, 2025Updated last year
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆67May 8, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆19Oct 17, 2024Updated last year
- ☆14Aug 1, 2024Updated last year
- C++17 Neural Network (NN), Convolutional Neural Network (CNN) and Deep Learning for Esp32 on IDF from scratch☆24Aug 23, 2023Updated 2 years ago
- RTOS for embedded systems☆15Sep 19, 2024Updated last year
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆18Dec 1, 2023Updated 2 years ago
- ☆22May 25, 2023Updated 3 years ago