UART implementation using verilog
☆39Feb 14, 2023Updated 3 years ago
Alternatives and similar repositories for UART
Users that are interested in UART are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆42Oct 3, 2025Updated 10 months ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆43Dec 5, 2019Updated 6 years ago
- A simple implementation of a UART modem in Verilog.☆193Nov 10, 2021Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository contains the design files of RISC-V Single Cycle Core☆86Dec 14, 2023Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆120Apr 27, 2024Updated 2 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆13Dec 31, 2024Updated last year
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆40Oct 29, 2023Updated 2 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- ☆18Aug 8, 2017Updated 9 years ago
- ☆29Apr 15, 2025Updated last year
- Structured UVM Course☆76Jan 4, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- UART design in SV and verification using UVM and SV☆58Nov 30, 2019Updated 6 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆33Oct 9, 2020Updated 5 years ago
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆18Mar 15, 2021Updated 5 years ago
- ☆21Nov 8, 2025Updated 9 months ago
- gem5 相关中文笔记☆16Dec 2, 2021Updated 4 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- Open source tools for IC design☆17Aug 4, 2026Updated 3 weeks ago
- Design and implementation of a reconfigurable FIR filter in FPGA☆16Sep 26, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆20Jun 24, 2021Updated 5 years ago
- ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write …☆25May 30, 2016Updated 10 years ago
- Wameedh Scientific Club Deep Learning for Computer Vision workshop repository.☆12Apr 2, 2024Updated 2 years ago
- ☆12May 8, 2022Updated 4 years ago
- Submission repo for Coderspree☆22Jul 10, 2022Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆49Mar 22, 2019Updated 7 years ago
- ☆15May 24, 2025Updated last year
- Verilog UART☆202Jun 4, 2013Updated 13 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- BSc. Project (UoW) - simulation of GSM and EDGE network modulation schemes (GMSK and 8PSK)☆17Jan 7, 2020Updated 6 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 15 years ago
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆10Sep 30, 2020Updated 5 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆74May 8, 2021Updated 5 years ago
- Single Cycle CPU using the RV32I Base Instruction set☆23Nov 5, 2025Updated 9 months ago
- ☆22May 25, 2023Updated 3 years ago
- ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.☆31Jul 3, 2026Updated last month