Open source FPGA silicon
☆319May 27, 2026Updated 2 weeks ago
Alternatives and similar repositories for aegis
Users that are interested in aegis are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A client implementation of the KISS TNC protocol, providing send and receive capability via a TCP/IP connection.☆12Jul 24, 2025Updated 10 months ago
- Python DSL that compiles element-wise expressions to parallel Rust. All CPU cores, zero serialization.☆44Mar 19, 2026Updated 2 months ago
- ☆171Jan 4, 2026Updated 5 months ago
- Isle FPGA Computer☆88Updated this week
- Odatix (previously Asterism) - An open-source design automation toolbox for FPGA/ASIC implementation☆25Apr 26, 2026Updated last month
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A Nushell environment for Nix - revived!☆32Jul 16, 2025Updated 10 months ago
- ☆11Jul 23, 2022Updated 3 years ago
- ☆27Jan 16, 2022Updated 4 years ago
- xMach (Mach4+Lites) cloned from Sourceforge CVS☆25May 28, 2026Updated last week
- ☆12Jun 4, 2021Updated 5 years ago
- plugins for pwnagotchi - tested on jay's 2.9.5.3+2.9.5.4 builds☆28Apr 25, 2026Updated last month
- Fast stackful fibers with a NUMA-aware work-stealing scheduler☆213Jun 3, 2026Updated last week
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆30Aug 15, 2025Updated 9 months ago
- sump3 logic analyzer☆43Feb 2, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Educational VHDL computer with a single-click toolchain for assembly, simulation, and execution on FPGAs☆46Updated this week
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆24Jan 24, 2026Updated 4 months ago
- Simple library to interface with Hitachi-compatible character LCDs for the Sipeed Tang Nano 4K Gowin FPGA board.☆10Aug 13, 2022Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆65Updated this week
- ☆13Dec 13, 2020Updated 5 years ago
- Training machine learning models on time-series data for the tinyml-esp repository.☆17Feb 13, 2024Updated 2 years ago
- Library of FPGA architectures☆33Apr 13, 2026Updated last month
- ☆14Aug 15, 2023Updated 2 years ago
- Papirus e-ink display for Direwolf TNC and Pi Zero☆14Jul 31, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- MR1 formally verified RISC-V CPU☆58Dec 16, 2018Updated 7 years ago
- Computer Engineering Senior Project. Machine Learning High Frequency Stock Trading Algorithm on an FPGA☆17Dec 4, 2019Updated 6 years ago
- Systems programming language with Python-like syntax and C-level performance. Compiles to native x86-64 machine code without external dep…☆23Apr 25, 2026Updated last month
- Python ACARS server☆12Mar 13, 2022Updated 4 years ago
- Generate Zynq configurations without using the vendor GUI☆30Jul 5, 2023Updated 2 years ago
- A webserver for on the fly delivery of Nix flake artifacts☆47Dec 11, 2025Updated 5 months ago
- ☆11Apr 19, 2021Updated 5 years ago
- Forth Programmable Breadboard☆11Jun 15, 2023Updated 2 years ago
- QQSPI Pmod-compatible 32MB PSRAM module☆16Sep 14, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆23Aug 3, 2024Updated last year
- This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primar…☆41Mar 28, 2022Updated 4 years ago
- A very simple SDRAM controller for FPGA written in Verilog. It exposes a SRAM-like interface to the rest of the FPGA fabric☆14Dec 4, 2018Updated 7 years ago
- AX.25 packet radio digipeater for linux☆13Nov 10, 2023Updated 2 years ago
- SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.☆500Mar 20, 2026Updated 2 months ago
- A configurable RTL to bitstream FPGA toolchain☆61Apr 24, 2026Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆215Updated this week