intel / rohd-vfLinks
The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
☆45Updated 8 months ago
Alternatives and similar repositories for rohd-vf
Users that are interested in rohd-vf are comparing it to the libraries listed below
Sorting:
- A hardware component library developed with ROHD.☆103Updated 2 weeks ago
- ☆97Updated 2 years ago
- SystemVerilog frontend for Yosys☆162Updated this week
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆24Updated 3 months ago
- SystemVerilog synthesis tool☆209Updated 6 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆139Updated last month
- ☆32Updated 8 months ago
- A dynamic verification library for Chisel.☆155Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated 2 months ago
- RISC-V Verification Interface☆103Updated 3 months ago
- WAL enables programmable waveform analysis.☆156Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated last week
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated this week
- A Fast, Low-Overhead On-chip Network☆227Updated last week
- ☆108Updated last month
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Updated 6 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- A SystemVerilog source file pickler.☆60Updated 11 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆126Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆110Updated 4 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Making cocotb testbenches that bit easier☆36Updated 2 months ago
- SystemVerilog support in VS Code☆141Updated 7 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆232Updated 2 weeks ago
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- Generic Register Interface (contains various adapters)☆129Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year