intel / rohd-vf

Related projects ⓘ

Alternatives and complementary repositories for rohd-vf

• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆81Updated this week
• intel / rohd-cosim
  Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
  ☆18Updated 8 months ago
• chipsalliance / uvm-verilator
  ☆75Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆137Updated 3 weeks ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆100Updated last month
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆44Updated 4 months ago
• accellera / uvm
  ☆42Updated 8 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆133Updated 5 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated 2 weeks ago
• accellera-official / uvm-core
  ☆57Updated 2 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆114Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆167Updated 2 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 2 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆76Updated 2 months ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆54Updated 3 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆104Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆142Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆146Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆58Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆46Updated this week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆146Updated last week
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆49Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆73Updated 7 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆136Updated 2 weeks ago