Alternatives and similar repositories for rohd-vf

Users that are interested in rohd-vf are comparing it to the libraries listed below

• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆97Updated this week
• chipsalliance / uvm-verilator
  ☆96Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆135Updated last week
• intel / rohd-cosim
  Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
  ☆23Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆120Updated this week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆201Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated this week
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month
• riscv-ovpsim / imperas-riscv-tests
  ☆181Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆97Updated last month
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆214Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated last month
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆151Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆152Updated 8 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆115Updated 3 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 3 weeks ago
• accellera-official / uvm-core
  ☆87Updated 10 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆71Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆73Updated last month
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆170Updated 7 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆161Updated last month