ycchen218 / EDA-IRdrop-PredictionLinks
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
☆31Updated 2 years ago
Alternatives and similar repositories for EDA-IRdrop-Prediction
Users that are interested in EDA-IRdrop-Prediction are comparing it to the libraries listed below
Sorting:
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆77Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆21Updated last year
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆50Updated 11 months ago
- ☆22Updated 11 months ago
- ☆47Updated last year
- Artificial Netlist Generator☆43Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆139Updated 3 months ago
- Analog Placement Quality Prediction☆24Updated 2 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- ☆12Updated last year
- ☆34Updated 4 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆52Updated 3 months ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆40Updated last month
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)☆404Updated 2 months ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆21Updated 2 years ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated last year
- ☆61Updated 3 weeks ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆139Updated 2 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆57Updated 8 months ago
- ☆58Updated 4 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆47Updated 4 years ago
- Machine Generated Analog IC Layout☆255Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆133Updated 2 months ago
- ☆25Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆56Updated 4 months ago
- Collection of digital hardware modules & projects (benchmarks)☆62Updated 3 weeks ago
- RePlAce global placement tool☆239Updated 5 years ago