ycchen218 / EDA-IRdrop-Prediction
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
☆27Updated last year
Alternatives and similar repositories for EDA-IRdrop-Prediction:
Users that are interested in EDA-IRdrop-Prediction are comparing it to the libraries listed below
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆22Updated 7 months ago
- Artificial Netlist Generator☆38Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆73Updated 8 months ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆19Updated 2 years ago
- VLSI EDA Global Router☆72Updated 7 years ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆35Updated 5 months ago
- ☆24Updated last year
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆119Updated 4 months ago
- ☆53Updated 4 years ago
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆34Updated 3 weeks ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆52Updated last month
- ☆17Updated 7 months ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆23Updated 7 months ago
- ☆22Updated 5 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆45Updated 3 months ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆37Updated 2 months ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆44Updated 3 months ago
- ☆29Updated 4 years ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆12Updated 3 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- ☆29Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆45Updated 7 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆131Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- Analog Placement Quality Prediction☆21Updated 2 years ago
- ☆77Updated 3 weeks ago
- SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)☆20Updated 2 years ago
- ☆43Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆138Updated 2 months ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆66Updated 5 months ago