ycchen218 / EDA-IRdrop-PredictionLinks
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
☆33Updated 2 years ago
Alternatives and similar repositories for EDA-IRdrop-Prediction
Users that are interested in EDA-IRdrop-Prediction are comparing it to the libraries listed below
Sorting:
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆53Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆82Updated last year
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆21Updated last year
- ☆13Updated last year
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- Artificial Netlist Generator☆44Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆142Updated 5 months ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆22Updated 2 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆55Updated 5 months ago
- ☆35Updated 4 years ago
- ☆23Updated last year
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)☆416Updated 4 months ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆42Updated 2 months ago
- ☆47Updated last year
- ☆59Updated 4 years ago
- Analog Placement Quality Prediction☆25Updated 2 years ago
- ☆89Updated 5 months ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated last year
- ☆26Updated 2 years ago
- Analog and mixed-signal automatic placer☆12Updated 2 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆52Updated 10 months ago
- ☆23Updated last month
- ☆17Updated last year
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Updated 4 years ago
- ☆62Updated 3 weeks ago
- ☆31Updated 3 years ago
- RePlAce global placement tool☆241Updated 5 years ago
- VLSI EDA Global Router☆76Updated 7 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- Machine Generated Analog IC Layout☆259Updated last year