ALINX ALTERA FPGA黑金开发学习板 CYCLONE IV 数电课设八位模型机
☆13Jul 27, 2018Updated 7 years ago
Alternatives and similar repositories for 8_bit_cpu
Users that are interested in 8_bit_cpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 东北大学编译原理课设实验☆27Dec 27, 2018Updated 7 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Using the Quartus II software, a OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the d…☆15Dec 29, 2016Updated 9 years ago
- 帮助新人入门开源,丰富简历☆12Mar 31, 2024Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆19Mar 4, 2026Updated last month
- A RISC-V virtual processor, written in Rust.☆19Apr 3, 2024Updated 2 years ago
- Formal verification tools for Chisel and RISC-V☆13Mar 29, 2026Updated last week
- Parametrized RTL benchmark suite☆25Feb 6, 2026Updated 2 months ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆52Mar 24, 2026Updated 2 weeks ago
- An open-source Simulation Trace Format specification☆16Nov 12, 2025Updated 4 months ago
- ☆22Aug 21, 2025Updated 7 months ago
- Synthesize Verilog to Minecraft redstone☆21Nov 9, 2024Updated last year
- ASON is a data serialization format that evolved from JSON, featuring strong numeric typing and native support for enumeration types.☆29Mar 31, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆29Mar 31, 2025Updated last year
- 基于verilog的数字时钟，数电课程设计☆39Sep 30, 2022Updated 3 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- Machine Learning-Enabled Compact Photonic Tensor Core based on Programmable Multi-Operand Multimode Interference☆13Sep 23, 2024Updated last year
- Qemu tracing plugin using SimPoints☆17Sep 12, 2024Updated last year
- ☆18Jul 12, 2024Updated last year
- HazardFlow: Modular Hardware Design of Pipelined Circuits with Hazards IMPORTANT: DON'T FORK!☆21Dec 5, 2024Updated last year
- Tiny verified SAT-solver☆30Jan 7, 2022Updated 4 years ago
- a Python framework for managing embedded HW/SW projects☆21Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- 🔭 interactively explore `onnx` networks in your CLI.☆26Jun 7, 2024Updated last year
- A fast and certifying solver for quantified Boolean formulas.☆26Apr 29, 2025Updated 11 months ago
- ☆24Jun 23, 2024Updated last year
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Feb 22, 2026Updated last month
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 3 months ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆30Sep 3, 2024Updated last year
- Chrome extension to download arXiv PDFs using the paper title as the filename.☆30Mar 20, 2026Updated 3 weeks ago
- Spectre V1 Proof-of-Concept Attack in the Rust Language☆29Apr 3, 2025Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Another Quarto reveal.js template extension inspired by Beamer Metropolis theme☆33May 10, 2024Updated last year
- PYNQ with Chisel and Rust☆26Jan 2, 2018Updated 8 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated 2 months ago
- A fast, brute force, automatic theorem prover for first order logic☆42Sep 20, 2024Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- ARCHIE is a QEMU-based architecture-independent fault evaluation tool, that is able to simulate transient and permanent instruction and d…☆33Mar 13, 2026Updated 3 weeks ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆26Mar 5, 2025Updated last year