apparentlymart / verilog-vga-simulator
Verilog VPI VGA Simulator using SDL
☆12Updated 10 years ago
Alternatives and similar repositories for verilog-vga-simulator:
Users that are interested in verilog-vga-simulator are comparing it to the libraries listed below
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 2 weeks ago
- Universal Advanced JTAG Debug Interface☆17Updated 10 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆29Updated 3 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆68Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 10 months ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- GDB Server for interacting with RISC-V models, boards and FPGAs☆21Updated 5 years ago
- Wishbone interconnect utilities☆39Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆35Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆62Updated 7 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆13Updated 2 months ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆23Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- CMod-S6 SoC☆40Updated 7 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆53Updated last year
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆27Updated 12 years ago
- iDEA FPGA Soft Processor☆16Updated 8 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 3 months ago
- ☆33Updated 2 years ago